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[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog编程中的基本程序，包括比较器，编码器，解码器，移位寄存器等-verilog programming in the basic procedures, including comparators, encoders, decoders, shift registers, etc.
Platform: | Size: 468992 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 各种基础的Verilog hdl实验的实验报告，包括D触发器，移位寄存器，选择器，译码器等等，有很详细的操作步骤，对于初学者很有用。-All based on Verilog hdl experiments are reported, including the D flip-flops, shift registers, selectors, decoders, etc., there are detailed steps, useful for beginners.
Platform: | Size: 3365888 | Author: yangshisong | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一些基本器件的实现，包括选择器，计数器，移位寄存器，多位寄存器以及各种测试模块-The realization of some of the basic devices, including the selection, counters, shift registers, a number of registers and a variety of test modules
Platform: | Size: 3072 | Author: 李辉 | Hits:

[VHDL-FPGA-Verilog] lab4

Description: this is a verilog code for shift registers
Platform: | Size: 228352 | Author: jacob | Hits:

[VHDL-FPGA-Verilog] password

Description: verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.
Platform: | Size: 578560 | Author: 陈振睿 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D flip-flop behavior, synchronous counters, asynchronous counters
Platform: | Size: 1067008 | Author: 城管111 | Hits:

[VHDL-FPGA-Verilog] Dchufaqi

Description: D触发器，移位寄存器，二进制转化器的verilog语言程序-D flip-flops, shift registers, binary converter verilog language program
Platform: | Size: 51200 | Author: 陈晗卿 | Hits:

[VHDL-FPGA-Verilog] Random-number-generator-verilog

Description: Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
Platform: | Size: 1177600 | Author: sndn_shr | Hits:

[VHDL-FPGA-Verilog] HWL_PRBS_GEN

Description: Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. PRBS. Verilog language
Platform: | Size: 1024 | Author: D | Hits:

[VHDL-FPGA-Verilog] Chip_74164

Description: 用Verilog语言描述了一款简单逻辑芯片的功能：74164-TTL八位串行入、并行输出移位寄存器-use Verilog to describe a simple chip 74164 with 8-Bit Serial In/Parallel Out Shift Registers
Platform: | Size: 2826240 | Author: WangYibin | Hits:

[VHDL-FPGA-Verilog] Parallel-To-Serial-Converter

Description: Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
Platform: | Size: 148480 | Author: Raz | Hits:

[VHDL-FPGA-Verilog] LSFR

Description: 线性反馈移位寄存器通常用于实现数据压缩电路中的基于循环冗余码校验的特征分析，应用于需要用伪随机二进制数的应用中。基于vivado的程序设计(Linear feedback shift registers are usually used to perform signature analysis based on cyclic redundancy check in data compression circuits, and are applied to applications requiring pseudorandom binary numbers. the program design based on vivado)
Platform: | Size: 103424 | Author: 准硬件工程师 | Hits:

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