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[WEB Code] UART(FPGA)

Description: 基于FPGA的串行通信UART控制器，采用VHDL语言编写，包含多个子模块。 在ISE或FPGA的其它开发环境下新建一个工程，然后将文档中的各个模块程序添加进去，即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Platform: | Size: 14758 | Author: 李浩 | Hits:

[Other resource] UART_ise7_bak

Description: 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control keypad mode).
Platform: | Size: 33179 | Author: lee | Hits:

[Documents] UART(FPGA)

Description: 基于FPGA的串行通信UART控制器，采用VHDL语言编写，包含多个子模块。 在ISE或FPGA的其它开发环境下新建一个工程，然后将文档中的各个模块程序添加进去，即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Platform: | Size: 14336 | Author: 李浩 | Hits:

[Software Engineering] FPGAEPP.files

Description: USB、串口、并口是PC机和外设进行通讯的常用接口，但对于数据量大的图像来说，若利用串行RS-232协议进行数据采集，速度不能达到图像数据采集所需的要求；而用USB进行数据采集，虽能满足所需速度，但要求外设必须支持USB协议，而USB协议与常用工程软件的接口还不普及，给使用带来困难。有些用户为了利用标准并行口(SPP)进行数据采集，但SPP协议的150kb/s传输率对于图像数据采集，同样显得太低。因此,为了采集数据量大的图像数据,本文采用了具有较高传输速率的增强型并行口协议(EPP)和FPGA，实现对OV7620CMOS图像传感器进行高速数据采集，它最高速率可以达到2Mb/s。-USB, serial port, parallel port is PC and peripherals used for the communication interface, But for the large volume of data images, if the use of Serial RS-232 data acquisition agreement, speed image data can not achieve the requirements for acquisition; using USB for data collection, can meet the required speed, But requirements must support USB peripherals agreement, and USB agreement with the commonly used engineering software interface is not universal, difficult to use. Some users to take advantage of standard parallel port (SPP), for data collection, But SPP agreement of 150 kb/s transfer rate for image data acquisition, the same is too low. Therefore, in order to collect large quantities of data image data, In this paper, the high transmission rate of enhanced parallel port proto
Platform: | Size: 81920 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] UART_ise7_bak

Description: 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control keypad mode).
Platform: | Size: 32768 | Author: lee | Hits:

[VHDL-FPGA-Verilog] FPGA+DSS+UART

Description: 用FPGA实现任意波形发生器的源代码，另外还包括FPGA实现UART，从而与MCU实现串行通信。-Using FPGA to achieve arbitrary waveform generator of the source code, including the FPGA also realize UART, in order to realize serial communication with the MCU.
Platform: | Size: 2048 | Author: zhuangxb | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
Platform: | Size: 3072 | Author: liaocongliang | Hits:

[VHDL-FPGA-Verilog] UARTReceiver

Description: serial communication using uart FPGA-based embedded system
Platform: | Size: 1024 | Author: hazwaj | Hits:

[VHDL-FPGA-Verilog] FpgaConfig_CS_20090508

Description: 自己写的一个使用单片机配置FPGA的上位机C#代码，使用串口通讯。-Wrote it myself, using a microcontroller to configure FPGA-Host Computer C# code, the use of serial communication.
Platform: | Size: 3061760 | Author: 胡小平 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 使用VHDL实现的串口通信程序，主要完成利用串口收发数据等功能 -Using the VHDL implementation of the serial communication program, primarily the completion of functions such as send and receive data using serial port
Platform: | Size: 5120 | Author: lionkurmose | Hits:

[VHDL-FPGA-Verilog] eda

Description: 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the design of DC motor PwM controller, DC motor speed control. Introduced with the Verilog HDL language programming controller PwM DC PwM generated module, serial communication module, steering adjustment module and other functions, the system is an external D/A converters and analog comparators, simple structure, high control precision, there a wide range of applications. Meanwhile, the introduction of PC control system control functions can be easily remote control the motor.
Platform: | Size: 4268032 | Author: 杨汉轩 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 实现FPGA的RS232串行通信，采用verilog语言编写，下载到芯片上就可以使用-FPGA implementation of the RS232 serial communication, using verilog language, can be downloaded to the chip using
Platform: | Size: 600064 | Author: shineson | Hits:

[VHDL-FPGA-Verilog] Serial-communication-with-PC

Description: 基于FPGA的用VHDL语言编写的串口与电脑通信程序-FPGA-based serial port using VHDL language and computer communication program
Platform: | Size: 494592 | Author: 飞虎队 | Hits:

[VHDL-FPGA-Verilog] fpga-uart

Description: 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
Platform: | Size: 15029248 | Author: cuit2009 | Hits:

[VHDL-FPGA-Verilog] fpga-uart-led

Description: 利用fpga实现串口通信，并通过通信实现led的点亮-Fpga implementation using the serial communication, and through communication to achieve the led lights
Platform: | Size: 334848 | Author: lumin | Hits:

[VHDL-FPGA-Verilog] 4_uart

Description: FPGA开发板 nios 下的串口通信 采用寄存器操作方式-FPGA development board serial communication using nios register operations
Platform: | Size: 3072 | Author: 肖申克 | Hits:

[VHDL-FPGA-Verilog] TXd_FIFO

Description: 用FPGA 串口通信发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA向通过max232电脑发送数据-The FPGA to send part of the code, serial communication, the FPGA chip using xilinx sptan3e can implement on FPGA send through max232 computer data
Platform: | Size: 1024 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] SPI

Description: 用Verilog语言实现FPGA串口通信(Using Verilog language to realize FPGA serial communication)
Platform: | Size: 15360 | Author: 柠檬琉璃夏 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 使用VHDL语言在vivado平台上编的串口通信的完整工程，并能用EGO1开发板成功验证(The complete project of serial communication is compiled on the vivado platform using VHDL language, and it can be successfully verified with the EGO1 development board.)
Platform: | Size: 697344 | Author: vmansus | Hits:
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