Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all. Platform: |
Size: 20480 |
Author:daiowen |
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Description: 这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm Platform: |
Size: 604160 |
Author:李成有 |
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Description: 用FPGA实现了RS232异步串行通信,所用语言是VHDL,另外本人还有Verilog的欢迎交流学习,根据RS232 异步串行通信来的帧格式,在FPGA发送模块中采用的每一帧格式为:1位开始位+8位数据位+1位奇校验位+1位停止位,波特率为2400。由设置的波特率可以算出分频系数,具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2). Platform: |
Size: 1024 |
Author:saibei007 |
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Description: RS232串口通信协议,verilog实现,通过FPGA完全调通。-RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass. Platform: |
Size: 3072 |
Author:dingsheng |
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Description: RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass Platform: |
Size: 2048 |
Author:dinsh |
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Description: 该程序为RS232串口通信的VERILOG程序,在FPGA上已通过验证,在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0 Platform: |
Size: 1024 |
Author:su |
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Description: 完整的RS232 Verilog源代码,支持波特率可调,支持调试命令,配合串口调试工具,可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform. Platform: |
Size: 13312 |
Author:弘历 |
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Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备,为测量和控制系统中整合FPGA 技术的
灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑
功能,您不需要任何的有关底层硬件描述语言(HDLs)的知识,如VHDL 或是Verilog,也不需要了解板
卡级硬件设计,就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外,LabVIEW还
可以让您轻松地集成图象采集/分析、运动控制,以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries. Platform: |
Size: 274432 |
Author:侯yl |
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Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings. Platform: |
Size: 6756352 |
Author:515666524 |
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Description: 无刷直流电机 VHDL VERILOG 控制,速度环,RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA Platform: |
Size: 741376 |
Author: |
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