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[Crack Hackregister

Description: register 和decode 对就的注册机的源码,VC-register and decode to on registration machine source code, VC
Platform: | Size: 15329 | Author: 张灵飞 | Hits:

[Other resourceregister reallocation

Description: 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Platform: | Size: 121641 | Author: 咱航 | Hits:

[ADO-ODBCregister-login-manager-system-base-on-authority-co

Description: 基于权限控制-登陆注册-register-login-manager-system-系统 数据库是SQL2000或者ACCESS 还没调试 可做参考 完整版的 到时可以联系transient126@126.com _——————免费 学习用的
Platform: | Size: 266777 | Author: transientlee | Hits:

[OtherHow to register and download OPNET 9.1

Description: How to register and download OPNET 9.1
Platform: | Size: 91608 | Author: vampirespit | Hits:

[ActiveX/DCOM/ATLreg

Description: Register/Unregister com server
Platform: | Size: 2048 | Author: 站长 | Hits:

[OS programCRegKey

Description: 处理Register项的类 -The class for dealing with register item
Platform: | Size: 2048 | Author: 站长 | Hits:

[SourceCoderegister

Description: 一个作业题:链表的建立,查找。-An operating title: the establishment list to find.
Platform: | Size: 2048 | Author: shijijiang | Hits:

[Crack Hackregister

Description: register 和decode 对就的注册机的源码,VC-register and decode to on registration machine source code, VC
Platform: | Size: 270336 | Author: 张灵飞 | Hits:

[Crack HackRegister

Description: 包括注册号生成软件、LIB、DLL 加密模块 各种语言调用加密模块的例子程序等-including registration generation software, LIB, DLL encryption modules in various languages called encryption module examples procedures
Platform: | Size: 184320 | Author: | Hits:

[VHDL-FPGA-Verilogregister reallocation

Description: 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Platform: | Size: 121856 | Author: | Hits:

[GIS programregister

Description: 32×32的寄存器堆,它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成,最低层次的模块是D触发器,中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器,顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法,先用行为建模方法建立低层模块,然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Platform: | Size: 4096 | Author: | Hits:

[Software EngineeringWM8976Path-and-register-Setting

Description: 详述了wm8976的内部结构以及各种外部接口的初始化代码-寄存器配置。附图说明。-Wm8976 detailed internal structure, as well as various external interface initialization code- register configuration. Please refer to Plan Description.
Platform: | Size: 544768 | Author: yaoqy | Hits:

[GIS programshift-register-sequences

Description: 一本介绍产生移位寄存器序列的经典书籍!欢迎下载阅读-Introduce a shift register sequence generated classic books! Welcome to download reading
Platform: | Size: 1974272 | Author: 李俊 | Hits:

[Other Web Coderegister

Description: extjs java oracle register page working
Platform: | Size: 423936 | Author: vipin | Hits:

[Otherregister

Description: 计算机组成原理实验通用寄存器组。仅供大家参考。-Computer Organization experimental general-purpose register group. Only for your reference.
Platform: | Size: 284672 | Author: 于洪宇 | Hits:

[Special Effectsregister

Description: Image registration used to register images.
Platform: | Size: 1024 | Author: thrasherx | Hits:

[Com PortRegister

Description: windows串口控件注册机,及源代码,小程序一个,需要注册控件代码的同学可参考。主要获取注册函数DllRegisterServer 地址-windows serial port control, RI, and source code, a small program, students need to register the control code can refer to. Get registered address of the main function DllRegisterServer
Platform: | Size: 1657856 | Author: Oscar | Hits:

[VHDL-FPGA-Verilogregister-vcode

Description: shift register verilog code
Platform: | Size: 6144 | Author: praveen | Hits:

[VHDL-FPGA-VerilogShift-register

Description: 两种移位寄存器——通用和桶形移位寄存器,用硬件描述语言Verilog编写,适合初学者。-Two kinds of shift register- common and barrel shift register in Verilog hardware description language, suitable for beginners
Platform: | Size: 2048 | Author: 李菲 | Hits:

[OtherRegister

Description: this code is by VHDL language for register ent counter register and
Platform: | Size: 375808 | Author: nasser | Hits:
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