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[Other resource] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。
Platform: | Size: 1104 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。-Synchronous read write RAM verilog. Through simulation modelsim se.
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] or1200_sopc

Description: 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram，最小系统soc。包括片上ram的软件系统（C语言编写）都有。但下载者要使用此系统需要很多工具链，搞soc的应该都装好了。绝对原创！用quartusII11.0在Altera DE2-115上验证通过，Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Right?
Platform: | Size: 31982592 | Author: 咖啡猫 | Hits:

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[Other resource] Synchronous_read_write_RAM

[VHDL-FPGA-Verilog] Synchronous_read_write_RAM

[VHDL-FPGA-Verilog] or1200_sopc

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