Description: sdram的vhdl实现
本文介绍了sdram的控制时序特征,并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies Platform: |
Size: 84992 |
Author:cxr |
Hits:
Description: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱:wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com Platform: |
Size: 339968 |
Author:李伟 |
Hits:
Description: 利用vhdl编写的双端口Ram程序,不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction Platform: |
Size: 1024 |
Author:孙敬辉 |
Hits:
Description:
基于VHDL编写的DDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller Platform: |
Size: 1031168 |
Author:wfs |
Hits:
Description: 基于VHDL编写的SDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller Platform: |
Size: 1013760 |
Author:wfs |
Hits:
Description: RAM读写控制器,用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram Platform: |
Size: 3072 |
Author:王欢 |
Hits:
Description: AHB接口的ram控制器,可靠性非常强。除了两个周期内发生读到写或写到读的极限情况(一般处理器设计中不会有这种传输方式),其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem Platform: |
Size: 1024 |
Author:Jasking Wu |
Hits: