Search - radar verilog

[VHDL-FPGA-Verilog] FPGA_radar

Description: 优秀硕士论文，基于FPGA的雷达信号模拟器设计，对学FPGA的，特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value
Platform: | Size: 749568 | Author: zhang | Hits:

[Scanner] dsp_radar

Description: radar detecttion in verilog
Platform: | Size: 23552 | Author: kasmi | Hits:

[VHDL-FPGA-Verilog] farrow

Description: 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
Platform: | Size: 7234560 | Author: 左洪成 | Hits:

[VHDL-FPGA-Verilog] antenna_position

Description: 本程序为船舶导航雷达天线方位部分的verilog程序，包含QPF工程。-This procedure for the marine navigation radar antenna part of the Verilog program, including QPF works.
Platform: | Size: 9242624 | Author: 鲁文芳 | Hits:

[VHDL-FPGA-Verilog] sp6ex14

Description: verilog,ISE工程。倒车雷达实例，每100ms产生1个超声波测距模块所需的10us高脉冲激励，并用数码管以16进制数据显示经过滤波处理的回响信号的高脉冲计数值（以10us为单位），与此同时，蜂鸣器根据障碍物远近，也会相应的发出不同频率的响声。-verilog, ISE project. Reversing radar instance, every 100ms high pulse generating 10us required an ultrasonic ranging module incentives, and with digital data in hexadecimal display through high pulse count value filter processing echo signals (in 10us units), and this Meanwhile, according to the obstacle distance buzzer will emit different frequencies corresponding sound.
Platform: | Size: 6226944 | Author: lyg | Hits:

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[VHDL-FPGA-Verilog] FPGA_radar

[Scanner] dsp_radar

[VHDL-FPGA-Verilog] farrow

[VHDL-FPGA-Verilog] antenna_position

[VHDL-FPGA-Verilog] sp6ex14

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