Search - quartusII 6.0

[ELanguage] Crack_QII61_b201

Description: Altera QuartusII 6.1 的License 生成工具软件。-Altera QuartusII 6.1 License generation of software tools.
Platform: | Size: 6768 | Author: 宋阅 | Hits:

[Other resource] shuzixitongshiyan

Description: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．实验1：Quartus入门实验2：简单的组合逻辑电路设计实验3：七段数码管显示实验4：BCD码显示及运实验5：触发器和计数器实验6：存储器的设计实验7：基于DE2 的SOPC系统开发附录：
Platform: | Size: 755392 | Author: yulieyar | Hits:

[Other resource] QuartusII

Description: 介绍Quartus II 6.0使用指南。哈尔滨工程大学信息与通信工程学院
Platform: | Size: 861269 | Author: zb | Hits:

[Other resource] uart

Description: 基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程
Platform: | Size: 5093955 | Author: 吕常智 | Hits:

[Other Embeded program] QuartusII_RAM

Description: 介绍了QUARTUSII中ram的应用，以及基于它的NIOS嵌入式小系统设计-were introduced QUARTUSII ram applications, and based on its small Nios Embedded System Design
Platform: | Size: 307200 | Author: 黎明 | Hits:

[ELanguage] Crack_QII61_b201

Description: Altera QuartusII 6.1 的License 生成工具软件。-Altera QuartusII 6.1 License generation of software tools.
Platform: | Size: 6144 | Author: 宋阅 | Hits:

[DSP program] quartusII_clock

Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
Platform: | Size: 7562240 | Author: 河南 | Hits:

[Other] AlteraQuartusII6.0crack

Description: Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
Platform: | Size: 6144 | Author: 王国华 | Hits:

[VHDL-FPGA-Verilog] Eda1

Description: 程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
Platform: | Size: 6144 | Author: haidong | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
Platform: | Size: 265216 | Author: haidong | Hits:

[Documents] QuartusII-warning-expression

Description: 此文章讲述了QuartusII里出现的大部分警告的处理方法!-This article describes QuartusII occurred in the majority of treatment methods of warning!
Platform: | Size: 7168 | Author: xiongxiaohui | Hits:

[VHDL-FPGA-Verilog] QuartusII

Description:
Platform: | Size: 861184 | Author: zb | Hits:

[Embeded-SCM Develop] Quartusdoc

Description: QuartusII的文件管理，关于QuartusII中各类文档的归类说明。-QuartusII document management, on various QuartusII classified documents indicate.
Platform: | Size: 9216 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
Platform: | Size: 5093376 | Author: 吕常智 | Hits:

[Software Engineering] sopc_2DBarcode

Description: 基于SoPC的嵌入式二维条码识读系统使用集成在QuartusII中的SoPC Builder开发组件配置生成片上系统,结合降噪处理、背景分离图像校正、图像二值化、码字识别、信号纠错等技术，处理由OmniVision OV7649 CCD产生的条码图像。-SoPC based embedded system uses two-dimensional bar code reader integrated in QuartusII development of SoPC Builder component configured to generate system-on-chip, combined with noise reduction treatment, the background separation image correction, image binarization, character identification code, the signal error correction technologies such as treatment by the OmniVision OV7649 CCD barcode images generated.
Platform: | Size: 69632 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] quartusII

Description: quartusII最新使用指南，帮你快速上手quartusII。-about quartusII
Platform: | Size: 209920 | Author: erik | Hits:

[VHDL-FPGA-Verilog] wt

Description: 扩频发射机的设计实现与仿真以QuartusII 7.2 为设计和仿真工具来实现直接序列扩频(DSSS)扩频发射机-Design and implementation of spread spectrum transmitter to QuartusII 7.2 and simulation for the design and simulation tools to achieve the direct sequence spread spectrum (DSSS) spread-spectrum transmitter
Platform: | Size: 180224 | Author: 王涛 | Hits:

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[ELanguage] Crack_QII61_b201

[Other resource] shuzixitongshiyan

[Other resource] QuartusII

[Other resource] uart

[Other Embeded program] QuartusII_RAM

[ELanguage] Crack_QII61_b201

[DSP program] quartusII_clock

[Other] AlteraQuartusII6.0crack

[VHDL-FPGA-Verilog] Eda1

[VHDL-FPGA-Verilog] EDA

[Documents] QuartusII-warning-expression

[VHDL-FPGA-Verilog] QuartusII

[Embeded-SCM Develop] Quartusdoc

[VHDL-FPGA-Verilog] uart

[Software Engineering] sopc_2DBarcode

[VHDL-FPGA-Verilog] quartusII

[VHDL-FPGA-Verilog] wt

[Other] Crack_patch_license

[File Format] QuartusII-free-of-charge-to-use-IP-Core

[Software Engineering] QuartusII-6.0

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