Description: 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using a DE2 development board, using the chip EP2C35F672C6. The focus of this experiment is to master the Quartus II design flow, methods, and debugging techniques, and each pin DE2 development board understand the meaning and use. Platform: |
Size: 586752 |
Author:xjnkasndx |
Hits:
Description: EP2C208C8 FPGA开发源代码（芯蓝C8板）
turn_on_led
点亮LED
sw_led
拨动开关控制LED
rider_led
跑马灯
water_led
流水灯
key_led_without_debounce
轻触开关控制LED，无按键去抖
key_led_with_debounce
轻触开关控制LED，有按键去抖
seg7x8_dynamic_disp
七段数码管动态显示
matrixKeyboard_seg7
测试矩阵键盘，七段数码管显示
beep_test
滴滴声，测试蜂鸣器
beep_matrixKeyboard
简易不同频率发声器
lcd1602_test
测试LCD1602显示
lcd1602_clock
简易时钟，LCD1602显示
vga_color_slip
VGA显示彩条
vga_char
VGA显示字符
uart_tx_test
串口发送测试
uart_rx_test
串口接收测试
ps2_keyboard_test
PS2键盘测试，LCD1602显示-# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation s design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
--------------------------------------------------------------------------#
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Full Version
# Date created = 09:05:11 March 14, 2010
#
#-------------- Platform: |
Size: 3846144 |
Author:wqc |
Hits:
Description: vga
This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation. Platform: |
Size: 219136 |
Author:jiang nan |
Hits:
Search - quartus ii 9.0 s