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[Develop Tools] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA / CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4329224 | Author: 小易 | Hits:

[Develop Tools] Quartus

Description: 上传一份cpld 开发工具，Quartus II 中文教程.pdf，供学习参考。
Platform: | Size: 893121 | Author: chaidong | Hits:

[VHDL-FPGA-Verilog] sopc

Description: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Platform: | Size: 8863744 | Author: 刘吉 | Hits:

[Books] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4328448 | Author: 小易 | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1024 | Author: 陈刚峰 | Hits:

[VC/MFC] Designing_with_Quartus_II_Exercises_Ver10_v4_1

Description: 它是CPLD的驱动程序，是我找了很多资料才找到的哦，一定要看-it CPLD driver, I find a lot of information they can find, um, look at the
Platform: | Size: 327680 | Author: xjofor | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[Embeded-SCM Develop] quartusII

Description: quartusII 中文使用手册，给广大cpld 及 fpga 开发用户使用，谢谢大家的支持。-Chinese quartusII user manual to the general development of CPLD and FPGA users, I would like to thank everyone
Platform: | Size: 2369536 | Author: hrbu | Hits:

[Books] FPGAusingall

Description: 针对CPLD的所有应用，使自己花了好长时间才整理出来，分类-CPLD for all applications, so that spent their time before finishing well out of classification
Platform: | Size: 16572416 | Author: 阚建峰 | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[Books] Quartus

Description: 上传一份cpld 开发工具，Quartus II 中文教程.pdf，供学习参考。-Upload a CPLD development tool, Quartus II Chinese Course. Pdf, for learning reference.
Platform: | Size: 892928 | Author: chaidong | Hits:

[VHDL-FPGA-Verilog] 7HzUUFHT

Description: altera公司cpld/fpga开发软件quartus2中文使用教程-altera company cpld/fpga development of software to use Chinese quartus2 Guide
Platform: | Size: 3098624 | Author: 郑洪波 | Hits:

[VHDL-FPGA-Verilog] Crack_QII8.0

Description: quartus 8 的内存注册机，已经试验过，非常好用，完全破解。-quartus 8 Zhuceji memory has been tested, very easy to use, completely broken.
Platform: | Size: 15360 | Author: 庄保国 | Hits:

[Other] DSP

Description: 学习fpga/cpld的书籍，介绍quartus 2及dsp builder的使用，-Learning fpga/cpld books, introduced quartus 2 and dsp builder use,
Platform: | Size: 14001152 | Author: 彭武军 | Hits:

[VHDL-FPGA-Verilog] quartus-train

Description: 这是一款CPLD的在线调试软件。能够满足用于学习者的一般要求。-This is a debugging software online CPLD. Be able to meet the general requirements for learners.
Platform: | Size: 3944448 | Author: xiaolai | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
Platform: | Size: 308224 | Author: 胡兵 | Hits:

[source in ebook] ADCCONVER

Description: 控制CPLD对AD7656进行采样，环境quartus-use the CPLD to control AD7656
Platform: | Size: 270336 | Author: 簿智明 | Hits:

[VHDL-FPGA-Verilog] Cymometer

Description: Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Platform: | Size: 585728 | Author: 石头 | Hits:

[VHDL-FPGA-Verilog] RS232_FIR

Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
Platform: | Size: 202752 | Author: jay | Hits:

[Windows Develop] 基于Quartus-II-的FPGACPLD开发

Description: 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)
Platform: | Size: 6297600 | Author: VVVX | Hits:
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