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[Other resource] ug_altpll

Description: altera公司的IP core，对于初学硬件描述语言，想要利用quartus软件自带的锁相环电路库函数实现自己想要的功能有些帮助-altera the IP core, for hardware description language learning, quartus want to use the software to bring their own PLL circuit to achieve the function they want to help some of the functions
Platform: | Size: 716143 | Author: 林德 | Hits:

[Other resource] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形
Platform: | Size: 807196 | Author: 许东滨 | Hits:

[Other] ug_altpll

Description: altera公司的IP core，对于初学硬件描述语言，想要利用quartus软件自带的锁相环电路库函数实现自己想要的功能有些帮助-altera the IP core, for hardware description language learning, quartus want to use the software to bring their own PLL circuit to achieve the function they want to help some of the functions
Platform: | Size: 715776 | Author: 林德 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[VHDL-FPGA-Verilog] vga_timing

Description: 此乃VGA驱动的详细源码，并配有PLL。使用Quartus II 开发。-This is a detailed source VGA driver with a PLL. Use Quartus II development.
Platform: | Size: 253952 | Author: 荣俊齐 | Hits:

[VHDL-FPGA-Verilog] PLLTEST

Description: Altera Quartus to Pll Source
Platform: | Size: 387072 | Author: Seo Dong hyeok | Hits:

[VHDL-FPGA-Verilog] pll

Description: 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Platform: | Size: 332800 | Author: 张宏伟 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
Platform: | Size: 216064 | Author: ad | Hits:

[Other] LPM

Description: LPM 是参数可设置模块库Library of Parameterized Modules 的英语缩写，Altera 提供的 可参数化宏功能模块和LPM 函数均基于Altera 器件的结构做了优化设计。在许多实用情况 中，必须使用宏功能模块才可以使用一些Altera 特定器件的硬件功能。例如各类片上存储 器、DSP 模块、LVDS 驱动器、嵌入式PLL 以及SERDES 和DDIO 电路模块等等。这些可 以以图形或硬件描述语言模块形式方便调用的宏功能块，使得基于EDA 技术的电子设计的 效率和可靠性有了很大的提高。设计者可以根据实际电路的设计需要，选择LPM 库中的适 当模块，并为其设定适当的参数，就能满足自己的设计需要，从而在自己的项目中十分方 便地调用优秀的电子工程技术人员的硬件设计成果。 LPM 功能模块内容丰富，每一模块的功能、参数含义、使用方法、硬件描述语言模块 参数设置及调用方法都可以在QuartusⅡ中的Help 中查阅到，方法是选择“Help”菜单中 的“Megafunctions/LPM”命令。-LPM
Platform: | Size: 1526784 | Author: lidandan | Hits:

[VHDL-FPGA-Verilog] CyclonePLL

Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。 -Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
Platform: | Size: 553984 | Author: 裴雷 | Hits:

[VHDL-FPGA-Verilog] pll_100M

Description: pll debug code,for quartus fpga,vhdl code for straxtix.
Platform: | Size: 3072 | Author: liuman | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
Platform: | Size: 1024 | Author: louxy | Hits:

[VHDL-FPGA-Verilog] test_sdram

Description: 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block, logic block read SDRAM, SDRAM modules package to read and write, read and write buffer FIFO module, serial module occurs. Altera-based engineering design of the Quartus II 10.1, the software can be used later.
Platform: | Size: 3128320 | Author: | Hits:

[VHDL-FPGA-Verilog] PLL

Description: quartus II中IP核的使用案例，在程序里边调用了PLL核进行时钟的管理。-Quartus II IP core use cases, called in the program inside the PLL core clock management.
Platform: | Size: 230400 | Author: 李桐 | Hits:

[Software Engineering] pll

Description: 用quartus自带的ip核生成的pll代码-use the ip core from quartus ii to generate the programme of PLL.
Platform: | Size: 3072000 | Author: 徐强 | Hits:

[Other] FPGA

Description: quartus软件自带的PLL的讲解，可实现波形的分频倍频等功能-Quartus software comes with the interpretation of the PLL, which can realize frequency waveform frequency division of The Times, and other functions
Platform: | Size: 565248 | Author: 安慧林 | Hits:

[VHDL-FPGA-Verilog] vip_ex1

Description: PLL例化和LED闪烁,quartus开发，可以参考-PLL cases and LED flashing, quartus development, can refer to
Platform: | Size: 3152896 | Author: peter | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真， 具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
Platform: | Size: 218112 | Author: 小猪仔521 | Hits:

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