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[Other resource] arm7-verilog

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 38050 | Author: 王云 | Hits:

[VHDL-FPGA-Verilog] t80

Description: Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
Platform: | Size: 41984 | Author: 吴毅 | Hits:

[VHDL-FPGA-Verilog] miniMIPS

Description: 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS- I structure of the processor, 32bit, von Neumann structure
Platform: | Size: 222208 | Author: tsm998 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARMCORE

Description: 用verilog语言实现的ARM7处理器的标准内核的源代码程序,nnARM, 具有很好的参考价值-using Verilog language of the standard ARM7 processor core source code procedures nnARM, who have a good reference value
Platform: | Size: 457728 | Author: 王晨语 | Hits:

[Other] arm7-verilog

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 37888 | Author: 王云 | Hits:

[MPI] controller

Description: MIPS处理器的控制verilog代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS control processor Verilog code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[Embeded-SCM Develop] multiprocessor

Description: verilog语言编写的多处理器的程序代码，用QII直接打开即可-Verilog language, multi-processor code, using qii can directly open
Platform: | Size: 2577408 | Author: 侯典华 | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for alu in RISC processor
Platform: | Size: 1024 | Author: John jose | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[VHDL-FPGA-Verilog] mmarm_EDACN

Description: 用FPGA实现ARM嵌入式处理器功能的Verilog源码及说明-FPGA with embedded ARM processor to achieve the functional description of Verilog source code and
Platform: | Size: 194560 | Author: 赵呈 | Hits:

[ELanguage] nnARM_tb01_09_02

Description: arm processor verilog code
Platform: | Size: 406528 | Author: manish kumar | Hits:

[ELanguage] nnARM_tb01_07_19

Description: verilog code for ope processor
Platform: | Size: 1002496 | Author: manish kumar | Hits:

[VHDL-FPGA-Verilog] Processor_alu

Description: this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
Platform: | Size: 4096 | Author: Yogesh PAtel | Hits:

[assembly language] fft

Description: vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project
Platform: | Size: 364544 | Author: tejaswini | Hits:

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

Description: 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
Platform: | Size: 7168 | Author: ZLS | Hits:

[VHDL-FPGA-Verilog] src

Description: 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
Platform: | Size: 4096 | Author: ray | Hits:

[VHDL-FPGA-Verilog] processor-vhdl

Description: 包内有dsp320vc33，dsp6211，dsp6415，dsp6713,hc11_core(附加Verilog代码),p89c51,std8980,zr36060的源码-Dsp320vc33 dsp6211 dsp6415, dsp6713 hc11_core (additional Verilog code), P89C51 std8980 ZR36060 the source package
Platform: | Size: 760832 | Author: xumeng | Hits:

[VHDL-FPGA-Verilog] chapter_listing

Description: Embedded SoPC Design with Nios II Processor and Verilog Examples
Platform: | Size: 657408 | Author: davido | Hits:
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