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[Other] EMC EM78系列单片机教程

Description: 第一章 EM78系列单片机简介 1 第二章 EM78系列单片机硬件结构……………………………………………………….3 2.1. 主要功能特点 3 2.2. EM78X56型号分类、命名方法及管脚功能说明 3 2.2.1. 型号分类(表2.1)： 3 2.2.2. 命名方法: 3 2.2.3. EM78X56管脚功能描述 4 2.3. EM78内部结构框图 4 2.4. 程序存储器和堆栈 5 2.4.1. 程序存储器 5 2.4.2. 堆栈 6 2.5. 数据存储器RAM结构 6 2.5.1. 工作寄存器 6 2.5.2. 特殊功能寄存器 8 2.6. TCC/WDT及预分频器Prescaler 11 2.7. I/O口（port5、port6） 12 2.8. EM87X56复位 14 2.8.1. 产生复位原因 14 2.8.2. 复位状态 14 2.8.3. 内部上电复位电路和电压检测器 16 2.8.4. 外部复位电路 17 2.9. 休眠状态和唤醒 18 2.10. 中断功能 19 2.10.1. 硬件中断
Platform: | Size: 767727 | Author: Asunny | Hits:

[Embeded-SCM Develop] expt53_dvf

Description: 基于fpga和sopc的用VHDL语言编写的EDA数控分频器-FPGA and SOPC based on the use of VHDL language EDA NC prescaler
Platform: | Size: 38912 | Author: 多幅撒 | Hits:

[VHDL-FPGA-Verilog] vhdl1

Description: VHDL经典案例源码 有至少20个经典案例,如:自动售货机,分频器-Classic case of VHDL source code at least 20 classic cases, such as: vending machines, prescaler
Platform: | Size: 168960 | Author: 卢卢 | Hits:

[Other] CD4013

Description: 用CD4013双D触发器做的脉冲4分频器，以及单键触模式灯开关介绍，只用一个触摸电极片，就能完成开灯和关灯，以及多个触摸式开关电路举例-CD4013 dual D flip-flop used to do pulse 4 prescaler, as well as touch-mode one-touch light switches, the only one touching the electrode films, will be able to complete the turn on the lights and the lights are turned off, and the touch switch circuit, for example
Platform: | Size: 254976 | Author: 魏臻 | Hits:

[VHDL-FPGA-Verilog] clk_2div

Description: vhdl语言编写的2分频器代码，简单易懂-VHDL language 2 prescaler code, easy-to-read
Platform: | Size: 1024 | Author: 张昆 | Hits:

[VHDL-FPGA-Verilog] 52_divider

Description: 一个可实现多倍（次）分频器VHDL源代码设计-Times to achieve a (sub) prescaler VHDL design source code
Platform: | Size: 1024 | Author: linew | Hits:

[VHDL-FPGA-Verilog] cnt4

Description: 四位计数器 计数器是数字系统中用得较多的基本逻辑器件。它不仅能记录输入时钟脉冲的个数，还可以实现分频、定时、产生节拍脉冲和脉冲序列等。例如，计算机中的时序发生器、分频器、指令计数器等都要使用计数器。 -Counter Counter 4 is used by digital systems more basic logic devices. It not only records the number of input clock pulse, but also realize frequency, timing, producing beats, such as pulse and pulse sequence. For example, the computer timing generator, prescaler, counters, such as instructions to use counters.
Platform: | Size: 20480 | Author: sy | Hits:

[assembly language] D53

Description: 编程将8253计数器0，计数器1的工作方式设定为方式2，用作分频器，定时器2工作在方式3，方波；定时器0的输出作为定时器1的输入，定时器1的输出作为定时器2的输入，定时器2的输出接在LED上，运行后可观察到该LED灯在不停的闪烁。 -Programming will be 8253 counter 0, counter 1 work set to Mode 2 for the prescaler, the timer 2 in the way of 3, square Timer 0 Timer 1 output as the input, timer 1 Timer 2 output as the input, timer 2, then the LED output, the run can be observed that the LED lights flicker in the non-stop.
Platform: | Size: 1024 | Author: 林夕 | Hits:

[VHDL-FPGA-Verilog] div

Description: 该源码为VHDL语言编写的分频器，在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated
Platform: | Size: 110592 | Author: | Hits:

[Other] clkdiv_6

Description: 分频器，用于时钟信号的分频及倍频，供专业人事学习研究使用-Prescaler for the clock signal frequency and octave, for study and research the use of professional personnel
Platform: | Size: 3072 | Author: liuyi | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] work4dvf

Description: 数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter adder design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.
Platform: | Size: 33792 | Author: lkiwood | Hits:

[VHDL-FPGA-Verilog] div_clk

Description: 主时钟为15.36MHz的带选通的8位输出分频器，可得到100Hz,120Hz,1kHz,10kHz的频率-Master clock for the 15.36MHz band strobe output 8-bit prescaler, can be 100Hz, 120Hz, 1kHz, 10kHz frequency
Platform: | Size: 1024 | Author: wangyongbing | Hits:

[VHDL-FPGA-Verilog] div5

Description: 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器）-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler)
Platform: | Size: 252928 | Author: zfc | Hits:

[VHDL-FPGA-Verilog] fen1to7

Description: 这是我在ISP编程实验中独立编写的一个采用行为描述方式实现的分频器，通过两个并行进程对输入信号CLK进行8分频，占空比为1:7-This is my ISP programming experiment in the preparation of an independent description of the use of behavior to achieve the prescaler, through two parallel processes on the input signal CLK to 8 minutes frequency, duty cycle 1:7
Platform: | Size: 27648 | Author: daisichong | Hits:

[SCM] Example1

Description: 本例展示了如何利用外设TIM2来产生四路频率不同的信号。 TIM2时钟设置为36MHz，预分频设置为2，使用输出比较-翻转模式（Output Compare Toggle Mode）。 TIM2计数器时钟可表达为：TIM2 counter clock = TIMxCLK / (Prescaler +1) = 12 MHz 设置TIM2_CCR1寄存器值为32768，则CC1更新频率为TIM2计数器时钟频率除以CCR1寄存器值，为366.2 Hz。因此，TIM2通道1可产生一个频率为183.1 Hz的周期信号。 同理，根据寄存器TIM2_CCR2 、TIM2_CCR3和 TIM2_CCR4的值，TIM2通道2可产生一个频率为366.3 Hz的周期信号；TIM2通道3可产生一个频率为732.4 Hz的周期信号；TIM2通道4可产生一个频率为1464.8 Hz的周期信号。 可以通过示波器观察各路输出-This example demonstrates how to use peripherals TIM2 to generate four different signal frequencies. TIM2 clock set to 36MHz, pre-divider is set to 2, the use of output compare- flip model (Output Compare Toggle Mode). TIM2 counter clock can be expressed as: TIM2 counter clock = TIMxCLK/(Prescaler+ 1) = 12 MHz set TIM2_CCR1 register value is 32768, then cC1 update frequency for TIM2 counter clock frequency divided by the value of CCR1 register for 366.2 Hz. Therefore, TIM2 channel 1 can generate a frequency of 183.1 Hz for the periodic signal. Similarly, under the register TIM2_CCR2, TIM2_CCR3 and TIM2_CCR4 value, TIM2 channel 2 can have a frequency of 366.3 Hz cycle signal TIM2 channel 3 can have a frequency of 732.4 Hz cycle signal TIM2 Channel 4 can produce a frequency of 1464.8 Hz cycle signal. Can be observed through the oscilloscope various output
Platform: | Size: 209920 | Author: chen | Hits:

[SCM] STM32+TIM

Description: 本例展示了如何设置TIM工作在输出比较-非主动模式（Output Compare Inactive mode），并产生相应的中断。 TIM2时钟设置为36MHz，预分频设置为35999，TIM2计数器时钟可表达为： TIM2 counter clock = TIMxCLK / (Prescaler +1) = 1 KHz 设置TIM2_CCR1寄存器值为1000， CCR1寄存器值1000除以TIM2计数器时钟频率1KHz，为1000毫秒。因此，经过1000毫秒的时延，置PC.06输出为低电平。 同理，根据寄存器TIM2_CCR2 、TIM2_CCR3和 TIM2_CCR4的值，经过500毫秒的时延，置PC.07输出为低电平；经过250毫秒的时延，置PC.08输出为低电平；经过125毫秒的时延，置PC.09输出为低电平。 输出比较寄存器的值决定时延的大小，当计数器的值小于这个值的时候，点亮与PC.06-PC.09相连的LED；当计数器的值达到这个值得时候，产生中断，在TIM2的4个通道相应的中断里，把它们一一关闭。-err
Platform: | Size: 218112 | Author: chen | Hits:

[VHDL-FPGA-Verilog] SHUZIMIAOBIAO

Description: 秒表的逻辑结构比较简单，它主要由、显示译码器、分频器、十进制计数器、报警器和六进制计数器组成。在整个秒表中最关键是如何获得一个精确的100Hz计时脉冲，除此之外，整个秒表还需要一个启动信号和一个归零信号，以便能够随时启动及停止。 秒表有六个输出显示，分别为百分之一秒，十分之一秒、秒、十秒、分、十分，所以共有6个计数器与之对应，6个个计数器全为BCD码输出，这样便于同时显示译码器的连接。当计时达60分钟后，蜂鸣器鸣响10声。 -Stopwatch logical structure is relatively simple, it mainly shows decoder, prescaler, decimal counter, alarm and six counter-band components. Throughout the stopwatch the most critical is how to get an accurate pulse 100Hz time, in addition, a whole also need a stopwatch start signal and a zero signal, in order to be able to start and stop at any time. Stopwatch six output shows that were hundredth of a second, one-tenth of seconds, seconds, 10 seconds, hours, very, so a total of six counters corresponding, 6 all counter-wide code for BCD output, making it easier for At the same time show decoder connections. When the time up to 60 minutes later, the buzzer sound of ringing 10.
Platform: | Size: 6144 | Author: 朱书洪 | Hits:

[Other] prescaler

Description: Source code to program precaler LMX2322 with microcontroller ATmega8
Platform: | Size: 22528 | Author: Tillman | Hits:

[VHDL-FPGA-Verilog] Prescaler-to-use-VHDL-design

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and integral crossover frequency. All can be achieved through Synplify Pro FPGA synthesizer manufacturer or integrated to form a circuit that can be used and verified in ModelSim.
Platform: | Size: 339968 | Author: liufei | Hits:
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