Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - prbs verilog

Search list

[VHDL-FPGA-Verilog] pseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[Books] prbs

Description:
Platform: | Size: 166912 | Author: 5656 | Hits:

[VHDL-FPGA-Verilog] prbsforip

Description: 本文设计了一种简捷而又高效的伪随机序列产生方法，最后通过统计对比，说名这种方法产生的随机序列不仅周期长 还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence generated by not only the long cycle and also has two well-randomness
Platform: | Size: 268288 | Author: 5656 | Hits:

[VHDL-FPGA-Verilog] prbs

Description: 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
Platform: | Size: 50491392 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DK-ECP3-SERDES-010

Description: 为verilog 的SERDES 使用程序。可以实现高速串行接口数据通信，时钟还原。-Verilog program for the use of the SERDES. For high-speed serial interface data communications, clock restoration.
Platform: | Size: 6337536 | Author: fpga_cn | Hits:

[VHDL-FPGA-Verilog] lfsr

Description: simple PRBS generator using verilog hdl
Platform: | Size: 1024 | Author: karthik | Hits:

[VHDL-FPGA-Verilog] PRBS

Description: 代码是伪随机数生成和检测的模块，用于通信行业的FPGA编程。包括VHDL和Verilog两种语言的版本。用于做接口测试。-This module generates or check a PRBS pattern.
Platform: | Size: 7168 | Author: jinse | Hits:

[VHDL-FPGA-Verilog] hdl

Description: Verilog code for the PRBS generator, checker and analyzer.-Verilog code for the PRBS generator, checker and analyzer.
Platform: | Size: 5120 | Author: rocketsingh | Hits:

[VHDL-FPGA-Verilog] prbs

Description: verilog 格式的prbs数据。可以用于对发射机和接收机的误码率的测试-verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
Platform: | Size: 1024 | Author: lexie | Hits:

[VHDL-FPGA-Verilog] HWL_PRBS_GEN

Description: Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. PRBS. Verilog language
Platform: | Size: 1024 | Author: D | Hits:

CodeBus www.codebus.net