Description: 为了测量 DVD的Jitter ,需要知道刻录时钟。针对 DVD 特殊的数据格式 NRZI,提出一个专用的时钟恢复系
统 ,用于从读出的 RF信号中恢复写时钟。这个系统采用基于锁相环的双环结构。介绍系统结构、各个模块的构成原理、数
学模型 ,并结合 Simulink 给出仿真结果。理论和实验证明 ,该系统既可作为测量 DVD Jitter 的硬件电路设计的参考 ,也可作
为软件设计的工具。-DVD to the Jitter measurement, the burning need to know the clock. DVD special against the NRZI data format, a dedicated clock to restore the system, From time for the RF signal was restored clock. The system based on the dual-loop PLL structure. On the structure, the various modules of the composition theory, mathematical model, and is integrated Simulink simulation results. Theory and experiment proved that the system can measure DVD Jitter as the hardware circuit design reference can also be used as the design of software tools. Platform: |
Size: 405956 |
Author:熊静 |
Hits:
Description: 为了测量 DVD的Jitter ,需要知道刻录时钟。针对 DVD 特殊的数据格式 NRZI,提出一个专用的时钟恢复系
统 ,用于从读出的 RF信号中恢复写时钟。这个系统采用基于锁相环的双环结构。介绍系统结构、各个模块的构成原理、数
学模型 ,并结合 Simulink 给出仿真结果。理论和实验证明 ,该系统既可作为测量 DVD Jitter 的硬件电路设计的参考 ,也可作
为软件设计的工具。-DVD to the Jitter measurement, the burning need to know the clock. DVD special against the NRZI data format, a dedicated clock to restore the system, From time for the RF signal was restored clock. The system based on the dual-loop PLL structure. On the structure, the various modules of the composition theory, mathematical model, and is integrated Simulink simulation results. Theory and experiment proved that the system can measure DVD Jitter as the hardware circuit design reference can also be used as the design of software tools. Platform: |
Size: 405504 |
Author:熊静 |
Hits:
Description: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
-This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Platform: |
Size: 399360 |
Author:张骅 |
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Description: 接收机同步PLL模型文件，可以采用matlab/simulink软件编辑操作，适合软件无线电的初学者以及其他相关行业。-Receiver synchronization PLL model file, you can use matlab/simulink software editing operation, suitable for beginners and other related software radio industry. Platform: |
Size: 14336 |
Author:dlbuaa |
Hits:
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