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[VHDL-FPGA-Verilog] video_from_opencore

Description: 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
Platform: | Size: 152576 | Author: 12 | Hits:

[VHDL-FPGA-Verilog] sARM7TM

Description: ARM7TM core源码，此码来自于opencore组织，此组织免费提供一些IP core，都是一些老外写的。-ARM7TM core source, the code from opencore organizations, this organization provided free IP core, are written by foreigners.
Platform: | Size: 70656 | Author: | Hits:

[VHDL-FPGA-Verilog] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 15360 | Author: 姚卫忠 | Hits:

[VHDL-FPGA-Verilog] opencore

Description: 基于FPGA的视觉采集系统的实现，verilog源码-FPGA-based visual collection system, verilog source
Platform: | Size: 2166784 | Author: www | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。 相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: | Size: 12288 | Author: 程浩武 | Hits:

[Other] fpga_noc.tar

Description: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Platform: | Size: 1664000 | Author: 黄锦辉 | Hits:

[Other] fpga_NOC_mpsoc

Description: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Platform: | Size: 1842176 | Author: 黄锦辉 | Hits:

[Other] m16c5x_latest.tar

Description: PIC的8位单片机的源码，芯片16CX的源代码，摘自opencore的源代码，真实可用的- This project demonstrates the use of a PIC16C5x-compatible core as an FPGA- based processor. It implements the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog timer.
Platform: | Size: 171008 | Author: zhang | Hits:

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