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[VHDL-FPGA-Verilogopb_vga

Description: 一个EDK下的用户IP核,进行OPB总线到VGA的转换-EDK under a user IP core, the OPB bus to VGA conversion
Platform: | Size: 12288 | Author: 曹晶 | Hits:

[VHDL-FPGA-Verilogmkjpeg.tar

Description: 用FPGA实现的JPEG编码器,可以直接使用,内含完成说明文档,经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • Two programmable Quantization tables • Hardcoded Huffman tables (luminance and chrominance) • 2.3 to 2.7 clock cycles per one input 24 bit pixel @ 50 Quality • OPB programming and data Host interface • 4:2:2 subsampling • Source code target independent, synthesizable RTL VHDL code • Detailed documentation
Platform: | Size: 21650432 | Author: | Hits:

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