Search - multiplexer vhdl

[Post-TeleCom sofeware systems] VHDL_multiplexer

Description: 个人认为比较使用的几个VHDL源码之四multiplexer的源码-personally think that the use of the relatively few VHDL source 4 multiplexer the source
Platform: | Size: 2048 | Author: xingqiba | Hits:

[Software Engineering] SOPC_MPEG2_trainsformer

Description: 论文题目：基于SOPC的MPEG2传输流复用器设计-Thesis topic: Based on SOPC the MPEG2 transport stream multiplexer design
Platform: | Size: 28672 | Author: 张贺 | Hits:

[VHDL-FPGA-Verilog] Multiplexer

Description: 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
Platform: | Size: 145408 | Author: maxpayne | Hits:

[VHDL-FPGA-Verilog] mux_reg

Description: VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] 16-1MUX

Description: 16 down to 1 Multiplexer in Vhdl
Platform: | Size: 65536 | Author: Abdullah | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Platform: | Size: 267264 | Author: kk | Hits:

[VHDL-FPGA-Verilog] multiplexersemultiplexer

Description: this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 91136 | Author: jatab | Hits:

[Modem program] MuxDemux_E1_E3

Description: Multiplexer and demultiplexer from E1 to E3 stream
Platform: | Size: 6144 | Author: sai | Hits:

[Other] cpu

Description: 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7), the program counter 8) address multiplexer
Platform: | Size: 440320 | Author: liuying | Hits:

[VHDL-FPGA-Verilog] Multiplexer

Description: Source code of multiplexer on VHDL. The compilation is done in Quartus II for Cyclone II.
Platform: | Size: 458752 | Author: Dave | Hits:

[VHDL-FPGA-Verilog] MuxDemux_E1_E3

Description: E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
Platform: | Size: 7168 | Author: qi | Hits:

[VHDL-FPGA-Verilog] active-hdl-vhdl-code

Description: this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
Platform: | Size: 1024 | Author: anmol | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk.
Platform: | Size: 4096 | Author: cccs | Hits:

[VHDL-FPGA-Verilog] vhdL

Description: VHDL多路选择器（使用case语句）-VHDL multiplexer (using case statement)
Platform: | Size: 13312 | Author: zhangxk | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言实现的多路选择器，分别有if、case等不同的方法-VHDL language with the multiplexer, respectively, if, case and other different ways
Platform: | Size: 2048 | Author: 周波 | Hits:

[VHDL-FPGA-Verilog] 83_multiplexer

Description: vhdl 语言开发程序比较详尽微处理器里面的部件-vhdl language development program inside the more detailed parts of the microprocessor
Platform: | Size: 2048 | Author: 王俊 | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: multiplexer unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.
Platform: | Size: 25600 | Author: android | Hits:

[VHDL-FPGA-Verilog] mux

Description: ABOUT MULTIPLEXER VHDL CODE
Platform: | Size: 8192 | Author: nandini | Hits:

[VHDL-FPGA-Verilog] The-VHDL-various-basic-code

Description: VHDL的各种基本代码包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus controllable counter, digital tube scanner , dual 2 1 state machine program!
Platform: | Size: 3696640 | Author: ai | Hits:

[File Format] multiplexer

Description: 4:1 multiplexer VHDL code
Platform: | Size: 11264 | Author: Pragya Sharma | Hits:

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[Post-TeleCom sofeware systems] VHDL_multiplexer

[Software Engineering] SOPC_MPEG2_trainsformer

[VHDL-FPGA-Verilog] Multiplexer

[VHDL-FPGA-Verilog] mux_reg

[VHDL-FPGA-Verilog] 16-1MUX

[VHDL-FPGA-Verilog] multiplexer

[VHDL-FPGA-Verilog] multiplexersemultiplexer

[Modem program] MuxDemux_E1_E3

[Other] cpu

[VHDL-FPGA-Verilog] Multiplexer

[VHDL-FPGA-Verilog] MuxDemux_E1_E3

[VHDL-FPGA-Verilog] active-hdl-vhdl-code

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 83_multiplexer

[VHDL-FPGA-Verilog] multiplexer

[VHDL-FPGA-Verilog] mux

[VHDL-FPGA-Verilog] The-VHDL-various-basic-code

[File Format] multiplexer

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