Search - moore machine

[VHDL-FPGA-Verilog] moore state_machine

Description: 这是一个moore状态机的典型程序，供初学者参考-This is a typical state machine moore procedure reference for beginners
Platform: | Size: 1024 | Author: 张云鹏 | Hits:

[VHDL-FPGA-Verilog] mo0re_FSM

Description: -- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[Embeded-SCM Develop] moore

Description: Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable signal OE.
Platform: | Size: 25600 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] MOORE

Description:
Platform: | Size: 190464 | Author: wang | Hits:

[VHDL-FPGA-Verilog] STATE1

Description: VHDL源代码，莫尔型状态机，使用VHDL语言编写-VHDL source code, Moore type state machine, the use of VHDL language
Platform: | Size: 3072 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] moore

Description: moore状态机,综合已通过，可放心使用！正式版。-moore state machine, the Composite has passed, can rest assured that the use of! The official version.
Platform: | Size: 117760 | Author: | Hits:

[JSP/Java] wuziqi

Description: java五子棋人机对战代码，电脑的AI还是可以的，希望大家喜欢-man-machine war Gobang java code, the computer AI can still hope you like
Platform: | Size: 551936 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] moore1

Description: moore 状态机的一个简单的事例，初学者很好的地实例！-moore state machine of a simple example for beginners to very good example!
Platform: | Size: 1024 | Author: liyanjun | Hits:

[VHDL-FPGA-Verilog] example2

Description: 状态机一般分为三种类型： Moore 型状态机：次态=f(现状，输入)，输出=f （现状）； Mealy 型状态机：次态=f(现状，输入)，输出=f （现状，输入）；混合型状态机。 -State machine is generally divided into three types: Moore-type state machine: sub-state = f (the status quo, input), output = f (status) Mealy type state machine: sub-state = f (the status quo, input), output = f ( the status quo, input) mixed state machine.
Platform: | Size: 25600 | Author: 汤化锋 | Hits:

[VHDL-FPGA-Verilog] vhdl_pgms

Description: Program for Counter, mealy machine, moore machine, ones counter, seven segment with zero blanking and shift register in VHDL.
Platform: | Size: 3072 | Author: Sivraj P | Hits:

[VHDL-FPGA-Verilog] moore

Description: moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
Platform: | Size: 295936 | Author: xiaowang | Hits:

[matlab] moore_algotithm

Description: 用moore排序法来最小化延迟的总工作数量。里面有程序代码的说明和一个算例-Moore s algorithmm minimizes the number of tardy jobs for the single machine problem.
Platform: | Size: 6144 | Author: 小胡 | Hits:

[VHDL-FPGA-Verilog] moore

Description: vhdl simulation code for moore machine
Platform: | Size: 84992 | Author: SP | Hits:

[VHDL-FPGA-Verilog] Ch8_11

Description: this is a verilog program for a moore machine
Platform: | Size: 457728 | Author: jacob | Hits:

[VHDL-FPGA-Verilog] Verilog_hw_problem2

Description: this is a verilog program for a moore machine
Platform: | Size: 319488 | Author: jacob | Hits:

[VHDL-FPGA-Verilog] State_Machine

Description: 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state machine.
Platform: | Size: 1551360 | Author: baoguocheng | Hits:

[VHDL-FPGA-Verilog] de_dect

Description: LIFT CONTR0LLER...DESIGNED WITH FINITE STATE MACHINE WITH MOORE MACHINE
Platform: | Size: 2048 | Author: siddarth | Hits:

[VHDL-FPGA-Verilog] Traffic-light-on-corssline-

Description: 本实验中主要应用了状态机以及减法器的设计原理。在状态连续变化的数字系统设计中，采用状态机的设计思想有利于提高设计效率，增加程序的可读性，减少错误的发生几率。同时，状态机的设计方法也是数字系统中一种最常用的设计方法。一般来说，标准状态机可以分为穆尔（Moore）机和米利（Mealy）机两种。在穆尔机中，其输出仅仅是当前状态值的函数，并且仅在时钟上升沿到来时才发生变化。米利机的输出则是当前状态值、当前输出值和当前输入值的函数。-In this experiment, the application of the design principles of the state machine and the subtractor. In a state of continuous change of the digital system design using the state machine design ideas to improve the design efficiency, increase the readability of the program, reduce the error probability of the occurrence. At the same time, the state machine design is also a digital system, a most commonly used design methods. Generally speaking, the state machine can be divided into two kinds of Moore (Moore) machine, and Miriam (Mealy) machine. Moore machine, the output is only a function of the current state value, and only the arrival of the rising clock edge when the change. The Milligan machine' s output is the current state value, the function of the current output value and the current input values.
Platform: | Size: 149504 | Author: 蒋溯南 | Hits:

[Industry research] mealay-machine-source-code

Description: melay moore machine code
Platform: | Size: 8192 | Author: ekta | Hits:

[VHDL-FPGA-Verilog] moore

Description: 此代码利用状态机的思想实现moore型的时序逻辑电路。-This code using state machine thought realize Moore type of sequential logic circuit
Platform: | Size: 1549312 | Author: 边茂宣 | Hits:

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[VHDL-FPGA-Verilog] moore state_machine

[VHDL-FPGA-Verilog] mo0re_FSM

[Embeded-SCM Develop] moore

[VHDL-FPGA-Verilog] MOORE

[VHDL-FPGA-Verilog] STATE1

[VHDL-FPGA-Verilog] moore

[JSP/Java] wuziqi

[VHDL-FPGA-Verilog] moore1

[VHDL-FPGA-Verilog] example2

[VHDL-FPGA-Verilog] vhdl_pgms

[VHDL-FPGA-Verilog] moore

[matlab] moore_algotithm

[VHDL-FPGA-Verilog] moore

[VHDL-FPGA-Verilog] Ch8_11

[VHDL-FPGA-Verilog] Verilog_hw_problem2

[VHDL-FPGA-Verilog] State_Machine

[VHDL-FPGA-Verilog] de_dect

[VHDL-FPGA-Verilog] Traffic-light-on-corssline-

[Industry research] mealay-machine-source-code

[VHDL-FPGA-Verilog] moore

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