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[Develop Tools] ispDesignExpert

Description: 第 一 节 ispDesignEXPERT 简 介 第 二 节 ispDesignEXPERT System 的 原 理 图 输 入 第 三 节 设 计 的 编 译 与 仿 真 第 四 节 ABEL 语 言 和 原 理 图 混 合 输 入 第 五 节 ispDesignEXPERT System 中 VHDL 和Verilog 语 言 的 设 计 方 法 第 六 节 在 系 统 编 程 的 操 作 方 法 第 七 节 ModelSim 的 使 用 方 法 附 录 一 ispDesignEXPERT System 上 机 实 习 题 附 录 二 ispDesignEXPERT System 文 件 后 缀 及 其 含 义-Introduction Section II, section I ispDesignEXPERT ispDesignEXPE RT System III schematic design input to the compilation and simulation fourth ABEL language and schematics mixed input System V ispDesignEXPERT VHDL and Verilog language the statement in section VI Design System Programming methods of operation of the sect ModelSim use is an appendix pDesignEXPERT System attachment that the plane Appendix 2 ispDesignEXPE RT System file extension and its meaning
Platform: | Size: 1292134 | Author: 吴忌 | Hits:

[Software Engineering] Modelsim-data

Description: Modelsim的教程，挺不错的，简单明了，希望对对大家有帮助-Modelsim curricula, they are good, clear and simple, and I hope to be helpful to everyone
Platform: | Size: 528413 | Author: 兜兜 | Hits:

[Books] MODELSIM SE V5.5D

Description: ise破解\MODELSIM SE V5.5D.zip-ideally crack \ MODELSIM SE V5.5D.zip
Platform: | Size: 4096 | Author: | Hits:

[Books] ispDesignExpert

Description: 第 一 节 ispDesignEXPERT 简 介 第 二 节 ispDesignEXPERT System 的 原 理 图 输 入 第 三 节 设 计 的 编 译 与 仿 真 第 四 节 ABEL 语 言 和 原 理 图 混 合 输 入 第 五 节 ispDesignEXPERT System 中 VHDL 和Verilog 语 言 的 设 计 方 法 第 六 节 在 系 统 编 程 的 操 作 方 法 第 七 节 ModelSim 的 使 用 方 法 附 录 一 ispDesignEXPERT System 上 机 实 习 题 附 录 二 ispDesignEXPERT System 文 件 后 缀 及 其 含 义-Introduction Section II, section I ispDesignEXPERT ispDesignEXPE RT System III schematic design input to the compilation and simulation fourth ABEL language and schematics mixed input System V ispDesignEXPERT VHDL and Verilog language the statement in section VI Design System Programming methods of operation of the sect ModelSim use is an appendix pDesignEXPERT System attachment that the plane Appendix 2 ispDesignEXPE RT System file extension and its meaning
Platform: | Size: 1292288 | Author: 吴忌 | Hits:

[Books] modelsim_se_tutor

Description: modelsim_se_tutorThis is a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). -modelsim_se_tutorThis is a set of notes I p ut together for my class Computer Architecture in 1990. Students had a project in which they had to model a microprocessor architecture of thei r choice. They used these notes to learn VHDL. Th e notes cover the VHDL-87 version of the languag e. Not all of the language is covered (about 95%) .
Platform: | Size: 2026496 | Author: 罗春晖 | Hits:

[Software Engineering] Modelsim-data

Description: Modelsim的教程，挺不错的，简单明了，希望对对大家有帮助-Modelsim curricula, they are good, clear and simple, and I hope to be helpful to everyone
Platform: | Size: 528384 | Author: 兜兜 | Hits:

[Other] Modelsim-manual

Description: Modelsim中文教程,我看有这方面需要的朋友很多，但是站内的资源太少，和大家共享一下吧！-ModelSim Chinese Course, I do have friends in this area which needs a lot, but the station
Platform: | Size: 701440 | Author: pc4190 | Hits:

[Other] In-systemProgrammableSolutions1

Description: 目 录 第 一 节ispDesignEXPERT 简 介 第 二 节ispDesignEXPERT System 的 原 理 图 输 入 第 三 节设 计 的 编 译 与 仿 真 第 四 节ABEL 语 言 和 原 理 图 混 合 输 入 第 五 节ispDesignEXPERT System 中 VHDL 和Verilog 语 言 的 设 计 方 法 第 六 节 在 系 统 编 程 的 操 作 方 法 第 七 节ModelSim 的 使 用 方 法 附 录 一ispDesignEXPERT System 上 机 实 习 题 附 录 二ispDesignEXPERT System 文 件 后 缀 及 其 含 义-Contents Section I Introduction Section II ispDesignEXPERT the ispDesignEXPERT System schematic design input Section III Section IV ABEL compiler and simulation language and schematic diagram in section V ispDesignEXPERT System hybrid input in VHDL and Verilog design language of section VI in the system programming method of operation to use the ModelSim section VII of Appendix 1 ispDesignEXPERT System-on internship title ispDesignEXPERT System Appendix II document and the meaning of the suffix
Platform: | Size: 531456 | Author: 史蒙克 | Hits:

[Program doc] modelsimjiaocheng

Description: 里面是一个简单的MODSIM的设计步骤!我感觉这对初学者来说,非常的好-There is a simple design steps MODSIM! I feel this is for beginners, very good
Platform: | Size: 486400 | Author: 段正伟 | Hits:

[VHDL-FPGA-Verilog] Mentor(Modelsim)

Description: 原言语名字是MODELSIM百问.是一些常见的使用过程中出现的问题.希望对大家有用处.谢谢.-The original language name is ModelSim hundred question. Is the use of some common issues arising in the course. I hope to have the usefulness of U.S.. Thank you.
Platform: | Size: 779264 | Author: madder | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] color_converter.tar

Description: 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助-This code different image color conversion between formats, such as XYZ <-> RGB, different standards of RGB <-> RGB and RGB <-> YCbCr conversion between packet contains code m file matlab simulation, VHDL code . v documents and ModelSim Simulation Testbench documentation, I believe everyone will certainly help
Platform: | Size: 339968 | Author: 王弋妹 | Hits:

[Other] modelsim_compile

Description: 该文档主要讲modelSim和ISE怎么进行编译，我也遇到了这个问题，折腾了好久才弄明白-The document stresses the main ModelSim and ISE how to compile, I have encountered this problem for a long time before tossing understood
Platform: | Size: 1024 | Author: qiyongqiang | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: modelsim開發 用於CABAC解碼-I don t konw
Platform: | Size: 440320 | Author: zengkaihuang | Hits:

[VHDL-FPGA-Verilog] modelsim-examples

Description: 这两个examples 的源码是modelsim 自带教程里面最重要的两个！但是其中一个（memory）在大多是安装文件目录下没有，但是又很有用，我找了好久才找到,PDF上说这几个文件在：<modelsim安装目录>\examples\memory\verilog下:dp_syn_ram.v,ram_tb.v,sp_syn_ram.v 但是找过的人都知道，一般的版本下面都没有这个源码。我分享一下，方便大家查找！-These two examples of the source is modelsim tutorial which comes with the two most important! But one of the (memory) is installed in most of the files directory does not, however, and very useful, I found a long time to find, PDF files, said these: <modelsim安装目录> \ Examples \ memory \ verilog under: dp_syn_ram.v, ram_tb.v, sp_syn_ram.v but had to find people know, the general version of the following do not have the source code. I share, to facilitate the search!
Platform: | Size: 3072 | Author: jjl | Hits:

[Technology Management] MODELSIM-dataset

Description: modelsim详细资料集，各种开发文档，希望对你有所帮助！-modelsim detailed data sets, a variety of development documents, I hope for your help!
Platform: | Size: 4546560 | Author: 刘云 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 很好的modelsim自学文件。有本人的理解，希望对大家有用-Good self modelsim file. There I understood, I hope useful
Platform: | Size: 389120 | Author: knl1247 | Hits:
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