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[Other resource] ModelSim_foundation

Description: 用实际例子介绍了仿真软件modelsim的基本使用方法，适用于初学者-with practical examples of simulation software modelsim use of the basic method applied to beginners
Platform: | Size: 96297 | Author: 刘素珍 | Hits:

[VHDL-FPGA-Verilog] ModelSim_foundation

Description: 用实际例子介绍了仿真软件modelsim的基本使用方法，适用于初学者-with practical examples of simulation software modelsim use of the basic method applied to beginners
Platform: | Size: 96256 | Author: 刘素珍 | Hits:

[VHDL-FPGA-Verilog] AdderEmodelSim

Description: altera Quartus II modelSim 自動模擬搭配，內有範例。 (含電路) -altera Quartus II modelSim with automatic simulation, there are examples. (With circuit)
Platform: | Size: 191488 | Author: 陳小龍 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[Other] Examples

Description: 几个简单的verilog代码，推荐用modelsim工具学习-A few simple Verilog code, recommended by ModelSim tools to learn
Platform: | Size: 24576 | Author: 王修杨 | Hits:

[FlashMX] SDRAM

Description: 典型实例13SDRAM读写控制的实现与Modelsim仿真-Typical examples of implementation 13SDRAM read and write control simulation with the ModelSim
Platform: | Size: 367616 | Author: 应 | Hits:

[Other] FPGA

Description: 由于目前所用到的FPGA器件以Altera的为主，所以下面的例子也以Altera为例，工具组合为 modelsim + LeonardoSpectrum/FPGACompilerII + Quartus，但原则和方法对于其他厂家和工具也是基本适用的。-Because of the current devices used to Altera' s FPGA-based, so the following examples to Altera as an example, the instrument portfolio for modelsim+ LeonardoSpectrum/FPGACompilerII+ Quartus, but the principles and methods of other manufacturers and is also the basic instrument applicable.
Platform: | Size: 31744 | Author: 黑月 | Hits:

[Software Engineering] HuaWei_FPGA_Design

Description: 华为FPGA设计流程说明 由于目前所用到的FPGA器件以Altera的为主，所以下面的例子也以Altera为例，工具组合为 modelsim + LeonardoSpectrum/FPGACompilerII + Quartus，但原则和方法对于其他厂家和工具也是基本适用的。-Huawei FPGA design flow as a result of the current devices used to Altera' s FPGA-based, so the following examples to Altera for example, tools for modelsim+ LeonardoSpectrum/FPGACompilerII+ Quartus, but the principles and methods and tools for other manufacturers is also basic application.
Platform: | Size: 31744 | Author: qinzhan | Hits:

[VHDL-FPGA-Verilog] skills_of_ModelSim

Description: modelsim使用技巧大全，包括使用教程，例子，心得等等。详细描述了如何通过modelsim进行仿真设计，是初学者需要的资料-Encyclopedia of use modelsim skills, including the use of tutorials, examples, experiences and so on. Described in detail how to design modelsim simulation is the need for information for beginners
Platform: | Size: 1627136 | Author: 二米阳光 | Hits:

[Windows Develop] testbench

Description: vhdl modelsim testbench examples-vhdl modelsim testbench for modelsim with vhdl examples
Platform: | Size: 2048 | Author: nono | Hits:

[VHDL-FPGA-Verilog] VHDL_fre_div

Description: 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider Design, including even frequency, duty cycle and 50 of non-50 duty cycle of the odd frequency, half-integer (N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of With the circuit, and on the ModelSim verification.
Platform: | Size: 322560 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] ModelSim-code

Description: 用modelsim以及systemC发在一些小例子和使用心得-Made with modelsim and systemC use in some small examples and experiences
Platform: | Size: 1139712 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] modelsim-examples

Description: 这两个examples 的源码是modelsim 自带教程里面最重要的两个！但是其中一个（memory）在大多是安装文件目录下没有，但是又很有用，我找了好久才找到,PDF上说这几个文件在：<modelsim安装目录>\examples\memory\verilog下:dp_syn_ram.v,ram_tb.v,sp_syn_ram.v 但是找过的人都知道，一般的版本下面都没有这个源码。我分享一下，方便大家查找！-These two examples of the source is modelsim tutorial which comes with the two most important! But one of the (memory) is installed in most of the files directory does not, however, and very useful, I found a long time to find, PDF files, said these: <modelsim安装目录> \ Examples \ memory \ verilog under: dp_syn_ram.v, ram_tb.v, sp_syn_ram.v but had to find people know, the general version of the following do not have the source code. I share, to facilitate the search!
Platform: | Size: 3072 | Author: jjl | Hits:

[VHDL-FPGA-Verilog] vga_modelsim

Description: 这是一个通过modelsim仿真通过的例子，学会如何仿真代码，程序思路清晰明了，易学习。-This is a adopted by the modelsim simulation examples, learn how simulation code, program ideas clarity, easy to learn.
Platform: | Size: 1487872 | Author: 徐凯 | Hits:

[VHDL-FPGA-Verilog] EP3C8020111219125810_ROM_OK5

Description: 采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct. This routine is very simple and clear, as DSP builder of the Getting Started Sample. Which has been included to generate good modelsim simulation Examples and simulation results.
Platform: | Size: 13917184 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] Chapter2

Description: Chapter2文件夹：（1）Quartus II 8.0软件实例讲解：1位加法器实验，完整的设计工程文件在Chapter2/adder文件夹下（2)ModelSim SE 6.0软件实例讲解：十进制计数器实验，完整的设计工程文件在Chapter2/test_counter_10文件夹下 -Chapter2 folder: (1) the Quartus II 8.0 software examples to explain: an adder experiment, a complete design engineering documents in Chapter2/adder folder (2) ModelSim SE 6.0 software instance to explain: decimal counter experiment, complete design engineering files in Chapter2/test_counter_10 file folder
Platform: | Size: 5167104 | Author: boyzone | Hits:

[VHDL-FPGA-Verilog] Debussy-learning

Description: Debussy仿真软件使用方法及配套的实例代码。很详细的介绍了Debussy软件的使用方法，结合Modelsim来使用-Debussy simulation software use and supporting examples of code. Very detailed description of the use of Debussy software, combined with Modelsim to use
Platform: | Size: 1326080 | Author: wyzg | Hits:

[VHDL-FPGA-Verilog] textio03

Description: 在QUARTUS II 下用 MODELSIM 仿真的例子，用TEXTIO文件进行仿真，带读取数据的文本文件，注释也比较详尽。对初学仿真有帮助。-In QUARTUS II with MODELSIM simulation examples, simulation with TEXTIO file, a text file with read data, comments are more detailed. Simulation helpful for beginners.
Platform: | Size: 326656 | Author: xuegamgma | Hits:

[Embeded-SCM Develop] ise_c8051

Description: r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the rom and ram, you can run the c code. Modelsim simulation scripts contained within the project, the work of the internal hardware can be observed when the program is running.
Platform: | Size: 6135808 | Author: woody.wu | Hits:

[Embeded-SCM Develop] ModelSim电子系统分析及仿真

Description: 此文档详细说明了如何利用Modelsim软件对FPGA逻辑代码进行功能仿真和时序仿真的方法，并通过相关例子进行讲解说明(This document explains in detail how to use Modelsim software to perform functional simulation and time series simulation of FPGA logic code, and explain how to use some examples.)
Platform: | Size: 48652288 | Author: ZSMCDUT | Hits:
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