Welcome![Sign In][Sign Up]
Location:
Search - memory sinusoidale wave vhdl code

Search list

[VHDL-FPGA-VerilogVHDL-ROM4

Description: 基于ROM的正弦波发生器的设计:1.正弦发生器由波形数据存储模块(ROM),波形发生器控制模块及锁存模块组成 2.波形数据存储模块(ROM)定制数据宽度为8,地址宽度为6,可存储 64点正弦波形数据,用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

CodeBus www.codebus.net