Search - max verilog

[Other resource] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232453 | Author: wjz | Hits:

[Other resource] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ
Platform: | Size: 212295 | Author: 杨轶帆 | Hits:

[Software Engineering] VerilogHDLshujicaiji

Description: 基于Verilog HDL设计的自动数据采集系统介绍了一种采用硬件控制的自动数据采集系统的设计方法，包括数字系统自顶向下的设计思路、Verilog HDL对系统硬件的描述和状态机的设计以及MAX+PLUSII开发软件的仿真。设计结果表明：该采集系统具有很高的实用价值，极大地提高了系统的信号处理能力。
Platform: | Size: 78230 | Author: 李进来 | Hits:

[Windows Develop] trafficontrol

Description: 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with the EP series of successful experiments board test
Platform: | Size: 113664 | Author: 礼拜 | Hits:

[MiddleWare] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232448 | Author: wjz | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[VHDL-FPGA-Verilog] an485_design_example

Description: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Platform: | Size: 312320 | Author: zhiqiang | Hits:

[Software Engineering] 2005-9-5-M8AY1EQBIPZD4SWW

Description: 介绍了一种采用硬件控制的自动数据采集系统的设计方法，包括数字系统自顶向下的设计思路、Verilog HDL对系统硬件的描述和状态机的设计以及MAX+PLUSII开发软件的仿真。设计结果表明：该采集系统具有很高的实用价值，极大地提高了系统的信号处理能力。-Introduce a hardware-controlled automated data acquisition system design methods, including digital systems top-down design, Verilog HDL description of system hardware and state machine design and MAX+ PLUSII simulation software. Design results show that: The acquisition system of high practical value, which greatly improve the system
Platform: | Size: 44032 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Platform: | Size: 975872 | Author: 杨林成 | Hits:

[VHDL-FPGA-Verilog] wb_rtc

Description: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Platform: | Size: 8192 | Author: 姓名 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] MAX-PLUSII-soft

Description: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Platform: | Size: 124928 | Author: 徐靖 | Hits:

[Software Engineering] 07302529

Description: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Platform: | Size: 244736 | Author: 翁浩达 | Hits:

[VHDL-FPGA-Verilog] SPIsend

Description: Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v!
Platform: | Size: 145408 | Author: Rick | Hits:

[VHDL-FPGA-Verilog] a_block_with_several_functions_with_Verilog_HDL.ra

Description: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。 -Verilog is the most widely used hardware description language.It can be used to the modeling, synthesis, and simulation stages of the hardware system design flow. With the scale of hardware design continually enlarging, describing the CPLD with HDL become the mainstream of designing ASIC and other IC.To comprehend Verilog HDL and get some knowledge of CPLD device, we design a block with several functions with Verilog HDL. This thesis is about to discuss the above there aspects: Introduce the EPF10K 10 of Flex 10K series producted by Altera Corporation simply. the software Max+plusⅡ,Design the block with several functions with Verilog HDL.
Platform: | Size: 482304 | Author: li | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Verilog HDL language taxi meter is designed so that it will have the time display, billing and simulated taxi start, stop, reset and other functions, and set up the dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the advantages of digital logic circuits. Source by the MAX+ PLUS Ⅱ software debugging, optimization, download EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system.
Platform: | Size: 211968 | Author: mindy | Hits:

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

Description: 来自于ALTERA官方网站。本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.
Platform: | Size: 291840 | Author: 无小品 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog 中文教學 1.簡介 2. Verilog 的模型 3. Verilog 的架構 4. MAX+plus II 的環境 5. 基本資料型態 6. 輸出入埠的宣告 7. 邏輯閘階層模型的敘述 8. 資料流模型的敘述 9. 行為模型的敘述 10. 編譯命令 11. 循序邏輯電路範例
Platform: | Size: 600064 | Author: bill | Hits:

[VHDL-FPGA-Verilog] crc7

Description: 以crc7为例进行UVM的验证 Part 1：搭建环境。本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by system verilog language)
Platform: | Size: 9063424 | Author: viviergan | Hits:

[ARM-PowerPC-ColdFire-MIPS] vivado

Description: 用中规模MSI基本逻辑功能模块实现关模比较器（要求分别使用中规模和语言实现）：功能要求：它的输入是两个8位无符号二进制整数X和Y，以及一个控制信号S；输出信号为1个8位无符号二进制整数Z。输入输出关系为：当S=1时， Z=min(X,Y)；当S=0时， Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).)
Platform: | Size: 10240 | Author: 瘾1581 | Hits:

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