Search - max - CodeBus

[VHDL-FPGA-Verilog] 基于FPGA的李沙育图形发生器

Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Platform: | Size: 791552 | Author: 孔玉 | Hits:

[Other] 足球1

Description: 3d max 作业这是一个简单的作业3d max 作业3d max 作业-3d max operation is a simple operation 3d max operations 3d max operations
Platform: | Size: 17408 | Author: leo | Hits:

[Other] 200211001401

Description: 3d max 作业这是用3D MAX 做的一个沙发还不错-This is done using the 3D MAX also a good sofa
Platform: | Size: 64512 | Author: leo | Hits:

[Books] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4328448 | Author: 小易 | Hits:

[VHDL-FPGA-Verilog] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[OpenGL program] pzr

Description: 在OpengGL中实现3ds max中的Pan, zoom in, zoom out, arc rotate功能。-OpengGL in achieving the 3ds max Pan, zoom in, zoom out, rotate function arc.
Platform: | Size: 263168 | Author: 熊有益 | Hits:

[Graph program] maxfilt2

Description: 图象处理的matlab程序，Two-dimensional max filter，希望有用-the Matlab image processing procedures, Two-dimensional max filter, useful
Platform: | Size: 1024 | Author: yuhanzhou | Hits:

[GUI Develop] PhysX_2.4.0_SystemSoftware

Description: PhysX是一个显卡图象处理软件，AGEIA为3ds max开发的physX插件可以使3ds max用户创建精细的物理模型并且在不脱离3ds max环境的情况下测试它们。-PhysX is a graphics image-processing software AGEIA for 3ds max physX development of the plug-in enables users to create 3ds max fine of Physics no model in 3ds max out the circumstances under testing.
Platform: | Size: 6409216 | Author: jkfd | Hits:

[3D Graphic] 50842922D

Description: 3ds max 入门学习教程，希望可以与大家交流交流-learning guide, we hope to share with the exchange
Platform: | Size: 9416704 | Author: ss | Hits:

[GUI Develop] MAX_II_board_schematics.pdf

Description: MAXII开发板原理图． Revision Index & Table of Contents MAX II and Pereipherals PCI USB and Power Supplies Prototyping Area-MAXII development board schematics. Revision Index
Platform: | Size: 240640 | Author: 赵天 | Hits:

[VHDL-FPGA-Verilog] MAX_II_board_schematics

Description: Altera MAX II 开发板原理图-Altera's MAX II development board schematics
Platform: | Size: 241664 | Author: 周宇 | Hits:

[AI-NN-PR] bayesfunction

Description: bayeserr - Computes the Bayesian risk for optimal classifier. ％ bayescln - Classifier based on Bayes decision rule for Gaussians. ％ bayesnd - Discrim. function, dichotomy, max aposteriori probability. ％ bhattach - Bhattacharya s upper limit of mean class. error. ％ pbayescln - Plots discriminat function of Bayes classifier.-bayeserr- Computes the Bayesian risk for o ptimal classifier. % bayescln- Classifier bas ed on Bayesian decision rule for Gaussians. Bayes% nd- Discrim. function, dichotomy. max aposteriori probability. % bhattach- Bhat tacharya s upper limit of mean class. error. pb% ayescln- Plots discriminat function of Bayes c lassifier.
Platform: | Size: 5120 | Author: 孟庆 | Hits:

[matlab] Turbocode

Description: 包括turbo码编译码程序，译码算法包括sova及max-log-map算法，并有完整链路验证其性能。-including turbo coding- decoding procedures, SOVA including decoding algorithm and max-log-map algorithm, and link integrity test its performance.
Platform: | Size: 13312 | Author: tanbo | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] 基于FPGA的李沙育图形发生器

[Other] 足球1

[Other] 200211001401

[Books] fpga 和 cpld入门教程

[VHDL-FPGA-Verilog] maxshiyan

[OpenGL program] pzr

[Graph program] maxfilt2

[GUI Develop] PhysX_2.4.0_SystemSoftware

[3D Graphic] 50842922D

[GUI Develop] MAX_II_board_schematics.pdf

[VHDL-FPGA-Verilog] MAX_II_board_schematics

[AI-NN-PR] bayesfunction

[matlab] Turbocode

[OpenGL program] manyou

[Other] VHDL-FPGA-clock

[OpenGL program] maxLOADER

[VHDL-FPGA-Verilog] shuzizhong05

[Graph program] 3Dsmaxcap

[Graph program] 3Dsmaxyagao

[VHDL-FPGA-Verilog] DigitalClockVHDL

CodeBus www.codebus.net