Description: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
-This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
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Author:张骅 |
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Description: C语言实现了数字锁相环的程序,不过程序比较复杂,得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model Platform: |
Size: 24576 |
Author:蔡科 |
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Description: 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全
数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable to all-digital phase-locked loop DPLL layout SPICE simulation, with the The model simulation results verified. Platform: |
Size: 259072 |
Author:dashu |
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Description: 参考Matlab提供的模块建立简化的三相锁相环的仿真模型,只保留必要的步骤,如abc-dqz只计算Vq,去除频率反馈模块和自动参数调整模块等。
建立单相锁相环的计算模型
简化单相锁相环的系统结构,保留必要的PI控制器等模块
验证并讨论输入信号频率在45-65Hz变化时设计的锁相环的动静态性能
仿真并分析三相输入信号包含谐波、不平衡和直流偏移时锁相环的锁相结果-Reference Matlab provides three-phase PLL module to establish a simplified simulation model, retaining only the necessary steps, such as abc-dqz counting only Vq, remove frequency feedback module and automatic parameter adjustment module. simulation and analysis of the three-phase input signal contains harmonics, unbalance and DC offset PLL phase-locked Results Platform: |
Size: 305152 |
Author:李航 |
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