Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。
原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。
因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-(
编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。
在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。
打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi Platform: |
Size: 14336 |
Author:Jawen |
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Description: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through Platform: |
Size: 147456 |
Author:Chen.Y.M |
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Description: 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的-Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~ Platform: |
Size: 104448 |
Author: |
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Description: NCO 在信号处理方面有着广泛的应用。而函数发生器是NCO 中的关键部分，本文基
于FPGA 用状态机和流水线方法实现了CORDIC 算法，并取代了传统的ROM 查找表法。
最后通过Quartus II 软件给出仿真结果，验证了理论的正确性。-NCO in the Signal Processing has a wide range of applications. The function generator is a critical part of NCO, the paper-based FPGA using state machine implementation of the Ways and pipelining CORDIC algorithm, and replaces the traditional ROM look-up table method. Finally through the Quartus II software give simulation results to verify the correctness of the theory. Platform: |
Size: 164864 |
Author:LEO |
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Description: DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter Platform: |
Size: 10240 |
Author:黄萌 |
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Description: 本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8
位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并
行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation. Platform: |
Size: 144384 |
Author:黑月 |
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Description: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door Platform: |
Size: 1024 |
Author:肖毅 |
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Description: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code Platform: |
Size: 2048 |
Author:niuqs |
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Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter. Platform: |
Size: 44032 |
Author:394177191 |
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Description: 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究
的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储
于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町
以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of waveforms of different frequency output, a key component of electronic test systems. In this study, full digital signal generator that is based on DDS technology of direct digital synthesis design, VHDL and C language using the method of combining, by looking up stored in ROM look-up table in a variety of standard waveform data, the cattle and the high frequency tone Hf accuracy of the sine wave, square wave, sawtooth and other signals used, and town to modify table data, an arbitrary signal generator Platform: |
Size: 268288 |
Author:姚木 |
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Search - look up table in vhdl