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[Other resource] leon2-1.0.30-xst.tar

Description: Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
Platform: | Size: 1398134 | Author: 笑雨 | Hits:

[ARM-PowerPC-ColdFire-MIPS] leon2-1.0.30-xst.tar

Description: Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
Platform: | Size: 1397760 | Author: 笑雨 | Hits:

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Platform: | Size: 687104 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Platform: | Size: 752640 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-gr-pci-xc2v3000

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.
Platform: | Size: 416768 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] leon3

Description: leon3 source code 虽然gaisler网站上有下载，但是提供此代码，希望能与更多的朋友一起学习leon-leon3 source code although gaisler website to download, but the provision of this code, would like to work with more friends with learning leon
Platform: | Size: 144384 | Author: CGF | Hits:

[VHDL-FPGA-Verilog] leon-2.2.tar

Description:
Platform: | Size: 379904 | Author: Jackson | Hits:

[VHDL-FPGA-Verilog] FPU

Description: Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
Platform: | Size: 696320 | Author: Ruchi | Hits:

[Other] grlib-netlists-1.1.0.tar

Description: leon for 3 fpu. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
Platform: | Size: 19076096 | Author: serg | Hits:

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