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Description: max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
Platform: | Size: 1135 | Author: 李清 | Hits:

[VHDL-FPGA-Verilogjcq

Description: max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
Platform: | Size: 1024 | Author: 李清 | Hits:

[VHDL-FPGA-Verilogjcq

Description: vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
Platform: | Size: 43008 | Author: 王晓虎 | Hits:

[VHDL-FPGA-Verilogjcq

Description: 哈尔滨工业大学计算机设计与实践实验 实验1 寄存器设计-Harbin Institute of Technology Design and Practice of Computer Experiment Design Experiment 1 register
Platform: | Size: 18432 | Author: 冯泽昊 | Hits:

[matlabjcq

Description: 匹配追踪和正交匹配追踪,利用贝叶斯原理估计混合logit模型的参数,用于信号特征提取、信号消噪,是信号处理的基础,MIMO OFDM matlab仿真,已调制信号计算其普相关密度,应用小区域方差对比,程序简单。- Matching Pursuit and orthogonal matching pursuit, Bayesian parameter estimation principle mixed logit model, For feature extraction, signal de-noising, Is the basis of the signal processing, MIMO OFDM matlab simulation, Modulated signals to calculate its density Pu-related, Application of small area variance comparison, simple procedures.
Platform: | Size: 4096 | Author: 胡文山 | Hits:

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