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[VHDL-FPGA-Verilogintfit

Description: 基于Farrow结构的平方内插器,其中输入为8位的小数插值相位和8位的输入数据,实现8位数据输出,仿真验证结果显示此种方法占用资源少。-Farrow structure based on the square interpolator, which enter the decimal for the 8-bit and 8-phase interpolation of the input data to achieve 8-bit data output, simulation results show that this method, fewer resources are occupied.
Platform: | Size: 1024 | Author: 徐爽 | Hits:

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