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[VHDL-FPGA-Verilog] I2Cslave

Description: i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试-i2c slave, this is the receiving end I2CBUS source code, from VERILOG languages, through integrated and debug
Platform: | Size: 1024 | Author: Xiaoyang Wang | Hits:

[VHDL-FPGA-Verilog] I2C_receiver

Description: 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
Platform: | Size: 2048 | Author: lj | Hits:

[VHDL-FPGA-Verilog] I2C_Slave

Description: I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
Platform: | Size: 596992 | Author: QinZhujun | Hits:

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