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[Graph program] modetable

Description: VESA TIMING标准模式表,VGA,YPBPR,HDMI，行频，场频，VTOTAL,HTOTAL设置-Table VESA TIMING standard mode, VGA, YPBPR, HDMI, line frequency, field frequency, VTOTAL, HTOTAL settings
Platform: | Size: 2048 | Author: p | Hits:

[Documents] DVI_HDMI

Description: DVI，HDMI接口时序，以及转换成其它如VGA和HDMI。DVI之间如何进行转换-DVI, HDMI interface, timing, and converted into other, such as VGA and HDMI. How to convert between DVI
Platform: | Size: 2020352 | Author: 汪翔 | Hits:

[Other] ADV7511_Hardware_Users_Guide

Description: ADI HDMI接口芯片USER GUIDE, 列出了内部寄存器、接口时序及输入输出格式等。可用于开发相关的控制软件-ADI HDMI interface chip USER GUIDE, lists the internal registers, interface timing and input and output formats. Can be used to develop the associated control software
Platform: | Size: 700416 | Author: xym | Hits:

[Graph program] modetable

Description: VESA TIMING标准模式表,VGA,YPBPR,HDMI，行频，场频，VTOTAL,HTOTAL设置-Table VESA TIMING standard mode, VGA, YPBPR, HDMI, line frequency, field frequency, VTOTAL, HTOTAL settings
Platform: | Size: 2048 | Author: 防身产品 | Hits:

[VHDL-FPGA-Verilog] Zed_vga_hdmi_720p

Description: 开发板zedboard上的hdmi的显示，采用开发工具ise，熟悉ideo的时序，推荐给大家-Hdmi display board zedboard on using development tools ise, familiar ideo timing and recommend it to everyone
Platform: | Size: 40960 | Author: 成功 | Hits:

[VHDL-FPGA-Verilog] hdmi_20130227

Description: (1)包含驱动HDMI编码芯片Sil9134的时序逻辑和寄存器初始化代码，输出测试图像格式为1080P@30Hz；（2）使用Vivado2013.3开发，硬件平台为威视锐Zing开发板，搭载Xilinx Zynq7020芯片。-(1) contains drivers HDMI encoder chip Sil9134 timing logic and register initialization code, output test image format 1080P @ 30Hz (2) use Vivado2013.3 development, hardware platform for Granville Sharp Zing development board, equipped with Xilinx Zynq7020 chips.
Platform: | Size: 24596480 | Author: 郝教授 | Hits:

[Other] CEA-861-D

Description: EDID Spec，里面有详细的HDMI Timing Table 描述，想学习EDID 相关timing的同学的福音来了-EDID Spec
Platform: | Size: 1381376 | Author: zhou ping | Hits:

[VHDL-FPGA-Verilog] hdmi_test

Description: HDMI时序及其仿真文件，可在显示器上显示色彩图形，时序标准为CEA861-D。-HDMI timing and simulation files, can be displayed on the monitor color graphics, timing standards for CEA861-D.
Platform: | Size: 1024 | Author: 李玉 | Hits:

[VHDL-FPGA-Verilog] HDMI_FPGA

Description: 该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
Platform: | Size: 5992448 | Author: 豪 | Hits:

[VHDL-FPGA-Verilog] 最新VGA时序标准

Description: 基于FPGA的图像处理时序标准，支持HDMI VGA DVI接口，非常有用。(FPGA-based image processing timing standard, support HDMI VGA DVI interface, very useful.)
Platform: | Size: 909312 | Author: 王月月 | Hits:

[Documents] AT070TN92_Final_Ver02_20101103_201208105952

Description: 群创7寸TFT触摸屏用户手册，准确掌握TFT时序图，VGA/AV/HDMI输入信号转图像。(Innolux 7-inch TFT touch screen user manual, accurately grasp the TFT timing diagram, VGA/AV/HDMI input signal to image.)
Platform: | Size: 1022976 | Author: 天荒地啦 | Hits:

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