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Description: 用verilog HDL实现自相关算法！
RTL级可综合代码！
通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
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Size: 3072 |
Author: ji |
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