Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - hdl fir filter

Search list

[Other resource] fir_finall

Description: 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
Platform: | Size: 1233 | Author: 刘东 | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] firOK

Description: fir滤波器的设计，此滤波器 Fs为44kHz,Fc为10.4kHz。-fir filter design, this filter Fs for 44kHz, Fc for 10.4kHz.
Platform: | Size: 987136 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] 16_FIR

Description: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Platform: | Size: 799744 | Author: yuming | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] verilogFir

Description: 基于Verilog+HDL的FIR数字滤波器设计与仿真 -Verilog+ HDL based on the FIR digital filter design and simulation
Platform: | Size: 167936 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] LMS_filter

Description: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Platform: | Size: 350208 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] FIR_chanbing

Description: FIR滤波器的verilog HDL语言编写的，希望对大家有用-FIR filter verilog HDL languages, we hope to be useful
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
Platform: | Size: 7241728 | Author: liu | Hits:

[Graph program] filter_dds_10.29_7.2

Description: 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
Platform: | Size: 1033216 | Author: chen | Hits:

[VHDL-FPGA-Verilog] FIR_Lowpass

Description: 用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
Platform: | Size: 796672 | Author: 李桐 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
Platform: | Size: 49152 | Author: 姚远 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 用Verilog HDL实现FIR滤波器的功能，文件包括Verilog HDL的源代码。-Using Verilog HDL realize the FIR filter function, the file includes Verilog HDL source code.
Platform: | Size: 15360000 | Author: 雪洁 | Hits:

[VHDL-FPGA-Verilog] FIRfilterverilogHDL

Description: FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter
Platform: | Size: 1024 | Author: L Liu | Hits:

[Other] fir

Description: A classic FIR filter implemented using Verilog HDL on the Xilinx software-A classic FIR filter implemented using Verilog HDL on the Xilinx software
Platform: | Size: 1024 | Author: DarkRofl | Hits:

CodeBus www.codebus.net