Description: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
-This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Platform: |
Size: 399360 |
Author:张骅 |
Hits:
Description: Verilog HDL语言编写的256色VGA显示程序，引脚分配适用于21EDA的EP2C8Q208开发板
程序中的PLL分频子模块为我上传的另一代码：PLL_50MHz_to_25MHz.rar-Verilog HDL language, 256-color VGA display program, pin assignment for the 21EDA the EP2C8Q208 development board programs. The PLL frequency sub-module is in another code I uploaded: PLL_50MHz_to_25MHz.rar Platform: |
Size: 737280 |
Author:LM |
Hits:
Search - hdl code for pll