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[VHDL-FPGA-Verilog] GFEMultiplierTaps

Description: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain Multiplier Verilog HDL source file of C program
Platform: | Size: 199680 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] GFEConsMulTaps

Description: 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain constant multiplier Verilog HDL source files of C procedures
Platform: | Size: 172032 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] mul

Description: 在gf(2^13)中，固定因子乘法器（基于自然基，0-128）-In gf (2 ^ 13), the fixed-factor multiplier (based on the natural base ,0-128)
Platform: | Size: 47104 | Author: 张凯斌 | Hits:

[VHDL-FPGA-Verilog] systolic

Description: 脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器-Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier
Platform: | Size: 2560000 | Author: chenyi | Hits:

[source in ebook] design_of_GF_mul

Description:
Platform: | Size: 2048 | Author: 石小磊 | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] Galois_field_multiplier_verilog_design

Description: 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
Platform: | Size: 2048 | Author: 海天之洲 | Hits:

[VHDL-FPGA-Verilog] GAFF

Description: 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
Platform: | Size: 2048 | Author: dayu1994 | Hits:

[VHDL-FPGA-Verilog] berlekamp_parallel

Description: The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis transformation circuits will be required. Fortunately for m = (3, 4, 5, 6, 7, 9, 10) the basis conversion from the dual to the polynomial basis - and vice versa - is merely a reordering of the basis coefficients [38]. For the important case m = 8 - for example the error-correcting systems used in CDs, DAT and many other applications operate over GF(28) - this basis conversion requires a reordering and two additions of the basis coefficients (Appendix C). In practice therefore, two additional XOR gates are required. Even including the extra hardware for basis conversions, the Berlekamp multiplier is known to have the lowest hardware requirements of all available bit-serial multipliers [24].
Platform: | Size: 156672 | Author: guctiida | Hits:

[Other] ABC

Description: 伽罗华域GF（q）乘法器设计 伽罗华域GF（q）乘法器设计-Jia LuoHuaYu GF (q) multiplier design
Platform: | Size: 2048 | Author: fangxiaolong | Hits:

[Software Engineering] ff_mul

Description: 伽罗华域GF（q）乘法器设计-Galois field GF (q) Multiplier
Platform: | Size: 2048 | Author: eee | Hits:

[VHDL-FPGA-Verilog] chengfaqi

Description: 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
Platform: | Size: 2048 | Author: 李永超 | Hits:

[VHDL-FPGA-Verilog] GF-(q)-multiplier-design

Description: 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
Platform: | Size: 1024 | Author: 吴敏 | Hits:

[VHDL-FPGA-Verilog] fpga_DESIGN_examples

Description: 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random sequence/integrator comb filter (CIC) Design/Galois field GF (q) Multiplier/divider design/common adder design/common multiplier design/RS (204,188) decoder design/CORDIC digital computer design
Platform: | Size: 27648 | Author: 老于 | Hits:

[VHDL-FPGA-Verilog] systolic_mul_D8_M193

Description: 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
Platform: | Size: 63488 | Author: yefeng | Hits:

[LabView] Galois-field-GF-(q)-.

Description: 伽罗华域GF（q）乘法器设计在FPGA板上的应用-Galois field GF (q) application of multiplier design on the FPGA board.
Platform: | Size: 2048 | Author: 高浚玮 | Hits:

[VHDL-FPGA-Verilog] RS(204-188)decoder_verilog

Description: 采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
Platform: | Size: 14336 | Author: 刘建涛 | Hits:

[VHDL-FPGA-Verilog] GF乘法器

Description: 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
Platform: | Size: 1024 | Author: 未曾走远 | Hits:

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