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[VHDL-FPGA-Verilog] adder

Description: 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。-The number of adder is produced and device. Addend and BeiJiaShu as input, and the device for output with binary for half a gal device. If BeiJiaShu and low addends, into digits for input, and and and carry for the output is for QuanJia device.
Platform: | Size: 302080 | Author: 张凯 | Hits:

[GDI-Bitmap] VB_VirtualGALengineTRY

Description: 大家可以参考一下用VB怎么编GAL引擎。-For your reference, how to use VB code GAL engine.
Platform: | Size: 1284096 | Author: 夏元中 | Hits:

[Other] Cupl

Description: CUPL语言是用于 GAL CPL可编程逻辑的编程语言，简单使用。文件包含教程和手册 -CUPL language is used for GAL CPL programmable logic programming language, simple to use. File contains tutorials and manuals
Platform: | Size: 4094976 | Author: jack | Hits:

[Embeded-SCM Develop] galblas1

Description: software to program gal chips
Platform: | Size: 531456 | Author: piet | Hits:

[Software Engineering] fgal

Description: examples and program to test .pld files for gal programming.
Platform: | Size: 32768 | Author: piet | Hits:

[File Format] calculate_bitrate

Description: calculate the bit rate of your gal chip
Platform: | Size: 61440 | Author: piet | Hits:

[VHDL-FPGA-Verilog] ep2

Description: 我在国外学习，使用CUPL编GAL，国内用的ABEL比较多，这方面资料比较少。压缩文件包含源码和仿真文件，仿真结果文件，可用wincupl或者PROTEL打开-CUPL EXAMPLE OF BUILDING A BASIC FSM IN GAL16V8
Platform: | Size: 3072 | Author: Junchuan Wang | Hits:

[Technology Management] draft-ietf-mpls-tp-gach-gal-00

Description: MPLS协议的QOS策略管理，讲述基本原理-MPLS Description QOS
Platform: | Size: 17408 | Author: 黎明 | Hits:

[Game Engine] sd_gpk_packer2

Description: 著名日文游戏School Days的资源打包器，自己编写，可以将汉化的文本或者资源重新打包为升级包或者汉化包。-packer program for the gal game school days.
Platform: | Size: 67584 | Author: growlanser | Hits:

[Game Engine] sd_gpk_unpacker

Description: 著名日文游戏School days的解包工具，可以提取出全部游戏资源。本人编写，可用于游戏汉化。-resource extractor for the gal game school days.
Platform: | Size: 77824 | Author: growlanser | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA开发全攻略_工程师创新设计宝典.FPGA 是英文 Field Programmable Gate Array 的缩写，即现场可编程门阵列，它是在 PAL、GAL、CPLD 等可编程器件的基础上进一步发展的产物。它是作为专用集成电路(ASIC)领域中的一种半定制电路而出现的， 既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。它是当今数字系统设计的主要硬件 平台，其主要特点就是完全由用户通过软件进行配置和编程，从而完成某种特定的功能，且可以反复擦写。在 修改和升级时，不需额外地改变PCB电路板，只是在计算机上修改和更新程序，使硬件设计工作成为软件开发 工作，缩短了系统设计的周期，提高了实现的灵活性并降低了成本，因此获得了广大硬件工程师的青睐。 -FPGA development Raiders _ engineers innovative design canon. The FPGA is the abbreviation of the English Field Programmable Gate Array, field programmable gate array, it is in PAL, GAL, the CPLD Further development of the product based on programmable devices. It appears as an application specific integrated circuit (ASIC) in the field of a semi-custom circuit, Not only to solve the lack of custom circuits to overcome the limited number of existing programmable devices gate shortcomings. It is the main hardware of today s digital system
Platform: | Size: 9625600 | Author: 辛璃 | Hits:

[DSP program] 10.LED

Description: 采用并行控制、动态显示方式：TMS320F28335 DSP数据线控制显示数据，通过74HC374对数据进行锁存；数码管公共端由另一片74HC374输出作为片选，分时控制数码管，达到动态显示的目的。74HC374控制信号由CPLD（xc95144xl）和GAL（一个PLD芯片）译码输出。并通过头文件（xdata.h）和修改CMD文件定义各个74HC374的地址为一个结构体，其中，“*Ex_smgc = (Uint16 *)0x206000 ”的高4位对应于4个数码管使能的锁存器地址。 “*Ex_smg = (Uint16 *)0x208000 ”对应于给数码管送数据的锁存器地址。 -TMS320F28335 use data s and use74hc374 lose and chin choose ,so control smg work.
Platform: | Size: 638976 | Author: yannaifan | Hits:

[Software Engineering] GalDevicesApplicationDesign

Description: 手把手教你学GAL器件应用设计 在深圳，一位 CPLD(可编程逻辑器件)设计人员的工资是月薪 1万元，而且还万金 难求。现在 FPGA／CPLD／ARM等芯片设计技术已越来越多地应用在产品开发中，本文 就是您通往芯片设计殿堂的起点。 -The GAL devices application design taught you to learn
Platform: | Size: 1687552 | Author: Alan Jeck | Hits:

[JSP/Java] GalParser

Description: Parse the result of a GAL command.
Platform: | Size: 1024 | Author: genpunfer | Hits:

[JSP/Java] ExchangeProvider

Description: ExchangeProvider provides real-time data from the Exchange server at the moment, it is used solely to provide GAL (Global Address Lookup) service to email address adapters. -ExchangeProvider provides real-time data from the Exchange server at the moment, it is used solely to provide GAL (Global Address Lookup) service to email address adapters.
Platform: | Size: 2048 | Author: soncewe | Hits:

[Other] FM

Description: GAL编译软件，生成JED文件，非常难得的东西-GAL compile software, it can generate the JED file, it very seldom
Platform: | Size: 14336 | Author: tian | Hits:

[Software Engineering] FPGA

Description: FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。它是作为专用集成电路（ASIC）领域中的一种半定制电路而出现的，既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。 -FPGA Field Programmable Gate Array is the English abbreviation, ie, field programmable gate arrays, it is a product on the basis of PAL, GAL, EPLD programmable devices such as further development. It is as ASIC (ASIC) in the field of the emergence of a semi-custom circuits, both to solve the lack of custom circuits, but also to overcome the limited number of the original gates of programmable devices shortcomings.
Platform: | Size: 144384 | Author: 李金光 | Hits:

[Linux-Unix] GalEmailAddressAdapter

Description: Email Address adapter that performs asynchronous GAL lookups.
Platform: | Size: 4096 | Author: gangbongheng | Hits:

[Software Engineering] cp

Description: le coefficient Cp Le coefficient de puissance a été introduit par la théorie de Betz. La limite de Betz indique que, pour les meilleures machines : bipale ou tripale, à axe horizontal, on ne récupère au maximum que 59 de l énergie due au vent, ce qui signifie que Cp max (théorique) est environ égal à 0,59. Pour une éolienne de puissance réelle, il est de l ordre de 0,3 à 0,4 au maximum. -le coefficient Cp Le coefficient de puissance a été introduit par la théorie de Betz. La limite de Betz indique que, pour les meilleures machines : bipale ou tripale, à axe horizontal, on ne récupère au maximum que 59 de l énergie due au vent, ce qui signifie que Cp max (théorique) est environ égal à 0,59. Pour une éolienne de puissance réelle, il est de l ordre de 0,3 à 0,4 au maximum.
Platform: | Size: 15360 | Author: FFG | Hits:

[Software Engineering] FPGA

Description: FPGA（Field－Programmable Gate Array），即现场可编程门阵列，它是在PAL、GAL、CPLD等可编程器件的基础上进一步发展的产物。它是作为专用集成电路（ASIC）领域中的一种半定制电路而出现的，既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。-FPGA (field programmable Gate Array), that is, field programmable gate arrays, it is a product of basic programmable devices in PAL, GAL, CPLD and so on the further development of the.
Platform: | Size: 177152 | Author: 小丸子 | Hits:
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