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Description: TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
Platform: |
Size: 3072 |
Author: zhangming |
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Description: This sample is a simple example on how to perform a glow effect by rendering into
an arbitrary size Frame Buffer Object (FBO).
The Glow effect is performed on a specific part of the screen and can be done only
on specific objects of the scene.
You can imagine using such a postprocessing effect in CAD/DCC to emphasize
some items from a selection or picking for example.-This sample is a simple example on how to perform a glow effect by rendering intoan arbitrary size Frame Buffer Object (FBO). The Glow effect is performed on a specific part of the screen and can be done onlyon specific objects of the scene.You can imagine using such a postprocessing effect in CAD/DCC to emphasizesome items from a selection or picking for example.
Platform: |
Size: 401408 |
Author: craig |
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Description: 主要实现视频文件中对每帧图像susan角点检测，程序比较清晰易读-The main achievement of the video file for each frame image susan corner detection, procedures legible
Platform: |
Size: 1024 |
Author: 东东 |
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Description: //建立顶级窗口
toplevel = XtVaAppInitialize[&app, "Frame", NULL, 0,
&argc, argv, NULL, NULL]
//建立Frame组件
n = 0
XtSetArg[args[n], XmNshadowType, XmSHADOW_ETCHED_IN] n++
XtSetArg[args[n], XmNshadowThickness, 4] n++
frame = XmCreateFrame[toplevel, "frame", args, n]
XtManageChild[frame]
Platform: |
Size: 1024 |
Author: xiaoran |
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Description: convert each frame in the yuv file into .bmp files
Platform: |
Size: 1024 |
Author: lauwah |
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Description: MSTAR03的数码相框的代码，可做读卡器，支持CARD，USB，个性化的界面哦，已经量产的-Digital Photo Frame MSTAR03 of the code reader can do in support of CARD, USB, personalized interface Oh, already in volume production of
Platform: |
Size: 3177472 |
Author: 黄耀鹏 |
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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: |
Size: 2048 |
Author: 张键 |
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Description: 完成从SDH telecom bus的38Mhz*4系统时钟和复帧提取出SDH的telecom bus的C1j1,spe,au指针 ，H4位置等SDH帧结构-SDH telecom bus from 38Mhz* 4 the system clock and rehabilitation SDH frame to extract the telecom bus of C1j1, spe, au pointer, H4 location SDH frame structure
Platform: |
Size: 1024 |
Author: leon |
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Description: 从sdh数据流中找到相应的帧，并将其帧头按照另一码率输出。-From the SDH data stream to find the corresponding frame, and another header in accordance with the output bit-rate.
Platform: |
Size: 8192 |
Author: 杨春 |
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Description: ,把代码的主线已经分析了出来,对代码中几个最难理解的地方(最难理解的地方就是帧的类型的判定,参考帧是如何管理的,一个16*16的块是采用到底需不需要分割,分割的话分成什么大小的,子块又采用何种预测方式,这些实际上就是整个编码的主线.)-, Put the main line of code has already been analyzed by the code in some places the hardest to understand (the hardest to understand is the place to determine the type of frame, reference frame is how to manage, a 16* 16 block is to be used in the end Do not need partition, partition, then what size is divided into sub-block mode prediction also adopted, which is in fact the main line of the entire coding.)
Platform: |
Size: 736256 |
Author: 刘定佳 |
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Description: End Point Detection algorithm using Variable frame rate
Platform: |
Size: 1024 |
Author: alok |
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Description: 基于QT的数码相框，实现图片的查看和一些操作-QT-based digital photo frame, picture of the view and implementation of some operations
Platform: |
Size: 2048 |
Author: charles |
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Description: avi compress programing ,the prog will compress the frame which captured by camera. and compression it
Platform: |
Size: 212992 |
Author: 莫大 |
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Description: library for sounds using frame buffer
Platform: |
Size: 1065984 |
Author: Feres |
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Description: Recent IDC research paper:
SPECIAL STUDY
Digital Photo Frame 2008-– 2012 Forecast.
Useful to people who wants to develop digital frame.
Platform: |
Size: 247808 |
Author: Andy |
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Description: 对以太帧进行手动封装，对封装好的帧解析各个字段-Ethernet frame to manually package and a good frame for the package to resolve the various fields
Platform: |
Size: 133120 |
Author: yaolijuan |
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Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
Platform: |
Size: 827392 |
Author: liu |
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Description: frameset 使用详细说明和参数详解 以及实现的小实例-frameset information
Platform: |
Size: 75776 |
Author: 李星 |
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Description: 基于Verilog语言的数字通信系统的帧同步的实现原理以及Verilog代码实现-Verilog language-based digital communications system, the realization of the principle of frame synchronization as well as the Verilog code
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Size: 481280 |
Author: 黄虎 |
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Description: 数位相框厂牌MARS主力IC-MR7910的FIRMWARE,SCH,DRIVER,SETUP,UNV文件，吐血奉献！-MARS Digital Photo Frame manufacturer of IC-MR7910 main FIRMWARE, SCH, DRIVER, SETUP, UNV paper, hematemesis dedication!
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Size: 7097344 |
Author: hongyun |
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