Search - fpga n

[Other resource] fpga

Description: 基于PXA270-S linux的FPGA实现。向LED_CONTROL写入n即得到n*0.1S的延时，LED闪烁的快慢程度发生变化。
Platform: | Size: 2976 | Author: 徐亚雪 | Hits:

[Other resource] n-thingeterroot

Description: 用MATLAB里的XILINX BLOCK, 支持FPGA算法, 实现开平方, 并且取整.当计算停止时, VALID为高电瓶.
Platform: | Size: 25365 | Author: zhang tian | Hits:

Description: 基于PXA270-S linux的FPGA实现。向LED_CONTROL写入n即得到n*0.1S的延时，LED闪烁的快慢程度发生变化。-Based on the PXA270-S linux realize the FPGA. LED_CONTROL write n to get n* 0.1S delay, LED blinking speed of the extent of change.
Platform: | Size: 3072 | Author: 徐亚雪 | Hits:

[Algorithm] 200628111717

Description: DFT(Discrete Fourier Transformation)是数字信号分析与处理如图形、语音及图像等领域的重要变换工具，直接计算DFT的计算量与变换区间长度N的平方成正比。当N较大时，因计算量太大，直接用DFT算法进行谱分析和信号的实时处理是不切实际的。快速傅立叶变换(Fast Fourier Transformation，简称FFT)使DFT运算效率提高1～2个数量级。其原因是当N较大时，对DFT进行了基4和基2分解运算。FFT算法除了必需的数据存储器ram和旋转因子rom外，仍需较复杂的运算和控制电路单元，即使现在,实现长点数的FFT仍然是很困难。本文提出的FFT实现算法是基于FPGA之上的，算法完成对一个序列的FFT计算，完全由脉冲触发，外部只输入一脉冲头和输入数据，便可以得到该脉冲头作为起始标志的N点FFT输出结果。由于使用了双ram，该算法是流型(Pipelined)的，可以连续计算N点复数输入FFT，即输入可以是分段N点连续复数数据流。采用DIF(Decimation In Frequency)-FFT和DIT(Decimation In Time)-FFT对于算法本身来说是无关紧要的，因为两种情况下只是存储器的读写地址有所变动而已，不影响算法的结构和流程，也不会对算法复杂度有何影响。-err
Platform: | Size: 59392 | Author: 吴庆庆 | Hits:

[VHDL-FPGA-Verilog] div

Description: 分频器是FPGA设计中使用频率非常高的基本单元之一。尽管目前在大部分设计中还广泛使用集成锁相环(如altera的PLL，Xilinx的DLL)来进行时钟的分频、倍频以及相移设计，但是，对于时钟要求不太严格的设计，通过自主设计进行时钟分频的实现方法仍然非常流行。首先这种方法可以节省锁相环资源，再者，这种方式只消耗不多的逻辑单元就可以达到对时钟操作的目的。偶数倍分频：偶数倍分频应该是大家都比较熟悉的分频，通过计数器计数是完全可以实现的。如进行N倍偶数分频，那么可以通过由待分频的时钟触发计数器计数，当计数器从0计数到N/2-1时，输出时钟进行翻转，并给计数器一个复位信号，使得下一个时钟从零开始计数。以此循环下去。这种方法可以实现任意的偶数分频。
Platform: | Size: 2048 | Author: 王子 | Hits:

[VHDL-FPGA-Verilog] n-thingeterroot

Description:
Platform: | Size: 25600 | Author: zhang tian | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Other Games] FPGA_NES_Version_1.0

Description: 用ＦＰＧＡ制作的ＮＥＳ游戏主机（８０后都知道的游戏主机）的ＶＨＤＬ代码，在ＱｕａｒｔｕｓＩＩ下编译通过。有兴趣的朋友一起交流。-FPGA produced with NES game console (80 after all know the game host) of the VHDL code, compiled under the QuartusII through. Are interested in sharing with friends.
Platform: | Size: 19456 | Author: submars | Hits:

[VHDL-FPGA-Verilog] FPGA-drivenLEDdisplay

Description: FPGA驱动LED显示:运用硬件描述语言（如VHDL）设计一个显示译码驱动器，即将要显示的字符译成8段码。由于FPGA有相当多的引脚端资源，如果显示的位数N较少，可以直接使用静态显示方式，即将每一个数码管都分别连接到不同的8个引脚线上，共需要8×N条引脚线控制.-FPGA-driven LED display: the use of hardware description languages (such as VHDL) design a display decoder driver, about to show the characters to 8 yards. Because there is a considerable number of FPGA-pin-side resources, if shown the median N less, you can direct the use of a static display, the upcoming digital tube are each separately connected to a different 8-pin line, required a total of 8 × N Article pin line control.
Platform: | Size: 1024 | Author: 王娟 | Hits:

[VHDL-FPGA-Verilog] FSKmodulationanddemodulation

Description: FSK调制与解调，整个设计基于ALTERA公司的QuartusⅡ开发平台，并用Cyclone系列FPGA实现。所设计的调制解调器具有体积小、功耗低、集成度高、软件可移植性强、扰干扰能力强的特点,符合未来通信技术设计的方向。-FSK modulation and demodulation, the entire design is based on ALTERA' s development platform Quartus Ⅱ, and Cyclone series FPGA implementation. Designed by the modem with a small size, low power consumption, high integration, software portability, and strong interference immunity characteristics consistent with the design of future communication technology direction.
Platform: | Size: 575488 | Author: 张继峰 | Hits:

[VHDL-FPGA-Verilog] cd4000x

Description: CD4000 双3输入端或非门+单非门 TI 　　CD4001 四2输入端或非门 HIT/NSC/TI/GOL 　　双4输入端或非门 NSC 　　CD4006 18位串入/串出移位寄存器 NSC 　　CD4007 双互补对加反相器 NSC 　　CD4008 4位超前进位全加器 NSC 　　CD4009 六反相缓冲/变换器 NSC 　　CD4010 六同相缓冲/变换器 NSC 　　CD4011 四2输入端与非门 HIT/TI 　　CD4012 双4输入端与非门 NSC 　　CD4013 双主-从D型触发器 FSC/NSC/TOS 　　CD4014 8位串入/并入-串出移位寄存器 NSC 　　CD4015 双4位串入/并出移位寄存器 TI 　　CD4016 四传输门 FSC/TI 　　CD4017 十进制计数/分配器 FSC/TI/MOT 　　CD4018 可预制1/N计数器 NSC/MOT -CD4000-cd4066
Platform: | Size: 2422784 | Author: 徐科峰 | Hits:

[DSP program] DSPFPGA

Description: 针对电梯数据采集数目较多和数据处理复杂等特点,提出了基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的电梯智能数据采集系统。在介绍了系统整体结构及各组成子模块后,给出了模块与器件之间硬件接口设计思路和架构,描述了整个系统的软件框架,设计了DSP、AD采样、网络通信和抗干扰等程序。整个系统在工程应用中易于实现,具有很好的推广价值-n accordance with the characteristic of elevator for the large number of data acquisition and handling data complicated, an el- evator data acquisition system based on digital signal processor (DSP) and field programmable gate array (FPGA) is given. After system structure and modules are introduced, the design of interfaces of the hardware and framework between modules and devices are provided, the software design used in the system is described, the DSP, AD sampling, network communication
Platform: | Size: 179200 | Author: 将建 | Hits:

[DSP program] DSP

Description: 利用TS201超高性能的计算处理能力以及FPGA支持的高速接口交换能力,实现了一种对算法的适应性强、结构扩展方便的通用信号处理板,设计了一种基于该通用信号处理板的米波雷达阵列信号处理系统,并以幅相校正、自适应旁瓣相消的算法实现为例,详细介绍了该阵列信号处理系统算法的实现方法。该系统运行稳定可靠,达到了系统的设计要求。-n this paper,multiple DSPs are adopted to design the array signal processing system.By utilizing the high processing ability of the TS201 and the high-speed data exchange ability supported by FPGA,a general array signal processing system with strong adaptability and easy-expansion ability is fulfilled for radar signal processing.Implementation of the algorithm,such as ASLC and calibration of magnitude and phase,is described in detail.The whole system works well,and meets the requirement of the system...
Platform: | Size: 429056 | Author: 将建 | Hits:

[Books] top1

Description: fpga，主要功能是实现n*n图像的旋转，源程序代码，-fpga, main function is to achieve the n* n image rotation, source code,
Platform: | Size: 1024 | Author: xutongxue | Hits:

[Program doc] STM-N-frame

Description: 介绍了SDH传输中的STM-N帧的定位和开销处理的一些关键信息，有助于FPGA编程实现开销处理和通道处理。-Describes the SDH transmission of STM-N frame and the positioning of some of the key information processing costs, help processing and FPGA programming overhead channel processing.
Platform: | Size: 135168 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

Description: 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的分频器。本次设计实现了包括整数、半整数和小数这三种不同类型分频器的分频，在设计过程中，系统主芯片采用EP1C6Q240C8，各个模块在QuartusⅡ上进行编程调试和仿真通过后，在GW48-SOPC上进行了下载。通过对各个部分测试后表明均能正确分频，完成了对系统的软件和硬件的设计，达到了系统的设计要求。 -Frequency divider refers to the frequency of the output signal as the input signal 1/N of electronic circuits. N is the frequency coefficient. In many electronic equipments such as the electronic clock, frequency synthesizers, which need different frequency signals work together and common way is to use the stability of the crystal oscillator as vibration source by converting the frequency components all needed. The frequency divider is a major means of conversion. In this paper, with the analytic study and review of trend basis of the technical frequency, a functional, reliable, economic and other design principles as the goal, this paper introduces a number of points frequency of the design and implementation based on FPGA. This design adopts the technology of EDA and hardware description language VHDL as logical description means of designing files. Under the environment of QuartusⅡ tools and the top-to-down approach, they build jointly a frequency divider by the basic modules base
Platform: | Size: 5120 | Author: 吴红梅 | Hits:

[SCM] FPGA

Description: 用c实现n点fft编程的源程序,经过仿真验证证明结果可行，大家下载后壳经行验证。-With c realize the source of the n-point FFT programming, through simulation results prove feasible, the validation of the shell through the line after you download.
Platform: | Size: 1024 | Author: qincheng | Hits:

[Program doc] Pradeep-N

Description: PCIE between altera DSP and FPGA
Platform: | Size: 12288 | Author: pradeep | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n

Description: UART code using VHDL for FPGA or ASIC
Platform: | Size: 10240 | Author: dani | Hits:

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