Search - fpga Digital clock

[Books] fpga时钟设计

Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将导致错误的行为，并且调试困难、花销很大。在设计PLD/FPGA时通常采用几种时钟类型。时钟可分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Platform: | Size: 402432 | Author: 与言 | Hits:

[VHDL-FPGA-Verilog] shzzh

Description: 这是在FPGA上实现的数字钟功能，用VERILOG语言编程，已功过编译，仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
Platform: | Size: 63488 | Author: 吴乔红 | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
Platform: | Size: 3072 | Author: 幸福 | Hits:

[Embeded-SCM Develop] clock

Description: 用verilog实现的数字跑表，下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
Platform: | Size: 492544 | Author: lizhiqiang | Hits:

[VHDL-FPGA-Verilog] clk_vhdl

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 652288 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] digitalwatch

Description: Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes-Describe: This is VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 92160 | Author: eric carmen | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] digital-clock

Description: Digital clock applicatian using seven segment with fpga xilinx
Platform: | Size: 2048 | Author: Ali Riza Simsek | Hits:

[VHDL-FPGA-Verilog] Digital-Clock

Description: 基于FPGA 的数字时钟SHEJI-Digital Clock in the FPGA
Platform: | Size: 1480704 | Author: lichenhai | Hits:

[VHDL-FPGA-Verilog] digital-clock-based-on-FPGA

Description: 基于ＦＰＧＡ的数字钟设计，编程语言是VHDL，编程环境是Quartus-digital clock based on FPGA
Platform: | Size: 3674112 | Author: lei | Hits:

[VHDL-FPGA-Verilog] FPGA-digital-clock-design

Description: 运用顶层设计思路设计好各个底层文件（VHDL代码），对各个底层文件进行功能仿真；采用原理图或者文本方法来实现顶层文件的设计，对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后，把顶层文件下载到实验箱的FPGA里边去，验证电路功能是否正确。具体时间用6位数码管来显示，具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of various underlying file
Platform: | Size: 2580480 | Author: 方可 | Hits:

[VHDL-FPGA-Verilog] digital-clock

Description: VHDL语言的数字时钟的设计，用于FPGA的数字时钟的设计。-VHDL language digital clock design, FPGA for digital clock design
Platform: | Size: 1035264 | Author: | Hits:

[VHDL-FPGA-Verilog] clock

Description: 本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。-This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading
Platform: | Size: 160768 | Author: 张伟 | Hits:

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[Books] fpga时钟设计

[VHDL-FPGA-Verilog] shzzh

[VHDL-FPGA-Verilog] vhdl--timer

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

[VHDL-FPGA-Verilog] clock

[Embeded-SCM Develop] clock

[VHDL-FPGA-Verilog] clk_vhdl

[VHDL-FPGA-Verilog] digitalwatch

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] digital-clock

[VHDL-FPGA-Verilog] Digital-Clock

[VHDL-FPGA-Verilog] digital-clock-based-on-FPGA

[VHDL-FPGA-Verilog] FPGA-digital-clock-design

[VHDL-FPGA-Verilog] digital-clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] FPGA-digital-clock-design

[VHDL-FPGA-Verilog] Based-FPGA-digital-clock-design

[VHDL-FPGA-Verilog] digital-clock

[VHDL-FPGA-Verilog] digital-clock

[MiddleWare] FPGA-digital-clock-and-stopwatch

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