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[Other resource] FM0

Description: 使用matlab生成FM0编码，下载到信号发生器输出。
Platform: | Size: 1035 | Author: LiuYu | Hits:

[VHDL-FPGA-Verilog] UHF+RFID中曼彻斯特及FM0编解码解决方案

Description: 曼彻斯特及FM0编解码解决方案
Platform: | Size: 2356818 | Author: hzz209 | Hits:

[RFID] FM0

Description: 使用matlab生成FM0编码，下载到信号发生器输出。-Using matlab to generate FM0 encoding, downloaded to the signal generator output.
Platform: | Size: 1024 | Author: LiuYu | Hits:

[Communication] FM0

Description: fm0 encoder and coder
Platform: | Size: 1024 | Author: lixinyou | Hits:

[ELanguage] FM0_encode

Description: 详细介绍了FM0编码，采用verilog编码语言-FM0 encoding, using verilog
Platform: | Size: 1024 | Author: kevin | Hits:

[Linux-Unix] iso18000

Description: 这是一篇超高频RFID的ISO18000协议的手持机读卡器的硕士论文，基于linux平台的，讲的很好！-This is a UHF RFID, ISO18000 protocol handheld reader master' s thesis, based on linux platform, speaking of the good!
Platform: | Size: 1494016 | Author: liguojin | Hits:

[RFID] RFIDreceiver

Description: 对RFID读写器接收模块的解调以及FM0解码进行了MATLAB仿真。首先我们对读写器接收到的信号进行仿真，里面附带着标签信息；其次对接收到的ASK信号进行相干解调；接着解调后的信号经过抽样判决，进行FM0解码。仿真结果可表明接收到的信号与发射的信号一致。-On the RFID reader receiver module FM0 decoding and demodulation and a MATLAB simulation. First of all we readers received signal simulation, which included the tag information followed by the received signal coherent ASK demodulation then demodulate the signal through the sample after the verdict, for FM0 decoding. Simulation results show that the received signal and the signal line emission.
Platform: | Size: 2048 | Author: 朵朵 | Hits:

[Crack Hack] FM0

Description: FM0解码程序，基于6B协议的读写器，对接收指令的解码 -FM0 decoding
Platform: | Size: 1024 | Author: 小木头 | Hits:

[matlab] FM0

Description: 用matlab实现的FM0(双相间隔码编码）编码-Matlab implementation of the FM0 (two-phase interval coding) encoding
Platform: | Size: 1024 | Author: 殷刘川 | Hits:

[Com Port] fm0

Description: 485的串口通信程序，已经调通，可以使用-485 console
Platform: | Size: 4468736 | Author: a | Hits:

[Software Engineering] UHF-RFID-Manchesterand-FM0-encode

Description: UHF+RFID中曼彻斯特及FM0编解码解决方案-The Manchester, UHF+RFID and FM0 encoding and decoding solutions
Platform: | Size: 2357248 | Author: 海涛 | Hits:

[VHDL-FPGA-Verilog] phase-locked-loop-implementation

Description: 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] decode

Description: 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] manfm

Description: Manchesteer-FM0 coding using verilog
Platform: | Size: 22528 | Author: Ram | Hits:

[File Format] FULLY-REUSED-VLSI-ARCHITECTURE-OF-FM0

Description: FULLY REUSED VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR DSRC APPLICATIONS
Platform: | Size: 122880 | Author: isi | Hits:

[Other] ASK+FM0

Description: fm0编码(fm0 encode)
Platform: | Size: 1024 | Author: ai珊珊 | Hits:

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