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[Other resource] equlizer

Description: 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integrated RTL circuit which contains 3 module FILTER, ERR_DECISION, ADJUST hope useful for all.
Platform: | Size: 23727 | Author: 陈为 | Hits:

[VHDL-FPGA-Verilog] equlizer

Description: 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integrated RTL circuit which contains 3 module FILTER, ERR_DECISION, ADJUST hope useful for all.
Platform: | Size: 23552 | Author: 陈为 | Hits:

[Other] zishiyinglvbodebiyesheji

Description: 论文针对数字通信系统中，由于码间串扰(ISI)和信道加性噪声的干扰，导致信号在接收端产生误码，设计了基于LMS算法的自适应均衡器(滤波器)，并通过硬件描述语言VHDL和现场可编程逻辑器件FPGA实现均衡器的硬件实现。是一篇标准的毕业论文,有需要的朋友可以拿来做参考-Thesis for digital communications systems, crosstalk due to inter-symbol (ISI) and additive noise channel interference, leading to signals generated in the receiver error, design algorithm based on LMS adaptive equalizer (filter), and through hardware description languages VHDL and Field Programmable Logic Device FPGA hardware equalizer realize realize. Is a standard thesis, there is a need to make friends can be used as reference
Platform: | Size: 2353152 | Author: YZ | Hits:

[Program doc] FPGAImplementationof16QAMDemodulator

Description: 描述了一个用于微波传输设备的16QAM接收机解调芯片的FPGA实现,芯片集成了定时恢复、载波恢复和自适应盲判决反馈均衡器(DFE),采用恒模算法(CMA)作为均衡算法。芯片支持高达25M波特的符号速率,在一片EP1C12Q240C8(ALTERA)上实现,即将用于量产的微波传输设备中。 -Describes a microwave transmission equipment for 16QAM receiver demodulator chip FPGA realization of an integrated chip timing recovery, carrier recovery and blind adaptive decision feedback equalizer (DFE), using constant modulus algorithm (CMA) as the equalization algorithm. Chip supports up to 25M baud symbol rate, in the midst of EP1C12Q240C8 (ALTERA) achieved for the upcoming production of microwave transmission equipment.
Platform: | Size: 281600 | Author: 萝卜 | Hits:

[matlab] equizer

Description: HART协议的均衡器设计 DCT LMS 设计 + 位同步设计，仿真证明了设计的有效性-HART protocol design DCT LMS equalizer design+ Bit synchronous design, simulation proves the validity of the design
Platform: | Size: 21504 | Author: 进正化 | Hits:

[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar

Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Platform: | Size: 14336 | Author: Arun | Hits:

[Special Effects] rls

Description: 是二阶RLS自适应均衡的实现，采用V—LOG编写而成，是从工程中截取的 可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly
Platform: | Size: 5120 | Author: 刘伟 | Hits:

[Mathimatics-Numerical algorithms] Adaptive_FIR_Equalizer_With_Continuous-Time_Wide-

Description: Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line
Platform: | Size: 2061312 | Author: asia | Hits:

[3G develop] Channel_Equalizer

Description: 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Platform: | Size: 226304 | Author: zhaohaishun | Hits:

[VHDL-FPGA-Verilog] fir_9222_sopc

Description: 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
Platform: | Size: 5911552 | Author: z | Hits:

[VHDL-FPGA-Verilog] IterativeDecodingofBinary

Description: In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder.
Platform: | Size: 1515520 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] VerilogLangRefManual

Description: Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.-Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.
Platform: | Size: 1283072 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] DLMS

Description: DLMS equalizer for qam
Platform: | Size: 3072 | Author: cyberia | Hits:

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