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[Other resource] EP2C5_SCH

Description: ep2c5q208c8开发板原理图（完整），pdf文件。
Platform: | Size: 444991 | Author: 王明 | Hits:

[SCM] EP2C5_SCH

Description:
Platform: | Size: 444416 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] FPGA-SRAMt-test

Description: 测试型号为EP2C5Q208C8的FPGA的RAM是否正常，按提示操作，并显示每步的测试结果-EP2C5Q208C8 test models for the FPGA' s RAM and whether it is normal, according to prompts, and display each step of the test results
Platform: | Size: 2048 | Author: 冀少威 | Hits:

[VHDL-FPGA-Verilog] MyLCD

Description: 基于ALTERA FPGA EP2C5Q208C8，针对LCD RT12864A-1的FPGA驱动程序-based on ALTERA FPGA EP2C5Q208C8,the driver of LCD RT12864A-1
Platform: | Size: 26624 | Author: 廖干洲 | Hits:

[VHDL-FPGA-Verilog] signal

Description: EP2C5Q208C8 verilog 产生m序列 50M晶振分频得到时钟，可以选择10种时钟- -！-EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
Platform: | Size: 1041408 | Author: | Hits:

[VHDL-FPGA-Verilog] NOIS_shizhong

Description: lcd1602 时钟显示键盘控制 可调 noios ii代码 EP2c5q208c8-lcd1602 时钟显示键盘控制
Platform: | Size: 11949056 | Author: 李刚 | Hits:

[Windows Develop] eEP22C5_SCCHp

Description: ep2c5q208c8开发板板原理图（完整），pdf文件。 -ep2c5q208c8 development Banban schematic (complete), pdf file.
Platform: | Size: 444416 | Author: 本质 | Hits:

[VHDL-FPGA-Verilog] Countdown

Description: 基于EP2C5Q208C8的数字时钟。数码管显示，按键调节控制。-Digital clock EP2C5Q208C8. Digital display, regulation and control buttons.
Platform: | Size: 780288 | Author: anmko | Hits:

[Software Engineering] pao

Description: 基于CycloneIII系列的FPGA，EP2C5Q208C8的数字跑表系统设计。-FPGA based on CycloneIII series EP2C5Q208C8 digital stopwatch system design.
Platform: | Size: 692224 | Author: zuozuo | Hits:

[VHDL-FPGA-Verilog] BT656PcolorBarPFPGA

Description: Altera的EP2C5Q208C8芯片上跑通，后端接tw2880芯片输出上TV，进行验证无误。 i_pclk是27Mhz输入时钟，o_pclk是27Mhz输出时钟；i_clkin是笔者用的开发板50Mhz时钟，只用于生成稳定的复位信号。-Ran on Altera' s EP2C5Q208C8 chip pass, after termination tw2880 chip output on the TV, to verify correct. i_pclk 27Mhz input clock, o_pclk 27Mhz output clock i_clkin author development board 50Mhz clock, only used to generate stable reset signal.
Platform: | Size: 2048 | Author: daxws | Hits:

[VHDL-FPGA-Verilog] Sonic_2

Description: FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚-Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin
Platform: | Size: 5686272 | Author: cager | Hits:

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