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[VHDL-FPGA-Verilog] write_io

Description: DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
Platform: | Size: 94208 | Author: hanmy | Hits:

[VHDL-FPGA-Verilog] write_rd

Description: 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
Platform: | Size: 91136 | Author: hanmy | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] FIFO_EMIF

Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Platform: | Size: 1480704 | Author: 徐成发 | Hits:

[VHDL-FPGA-Verilog] xapp753

Description: FPGA Interface to the TMSC6000 DSP Platform Using EMIF
Platform: | Size: 1651712 | Author: jhjkhjnh | Hits:

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