Search - elevator in verilog

[Other resource] dianti

Description: Verilog在maxpuls2下开发的电梯控制器的文档（包括代码），其中说明十分详尽-Verilog maxpuls2 under development in the elevator controller files (including code), It showed very detailed
Platform: | Size: 74200 | Author: 余远恒 | Hits:

[VHDL-FPGA-Verilog] crc_16

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] dianti

[VHDL-FPGA-Verilog] verilog_dianti

Description: 一组两个电梯的控制器，希望对初学Verilog硬件描述语言的人有帮助。-One group of two elevator controller, in the hope of learning Verilog hardware description language help.
Platform: | Size: 3072 | Author: zz | Hits:

[VHDL-FPGA-Verilog] lift_controler-verilog

Description: 电梯控制程序！！ verilog 描述的-Elevator control procedures! ! described in verilog
Platform: | Size: 664576 | Author: pan | Hits:

[VHDL-FPGA-Verilog] NewFolder

Description: these are the codes written in verilog which are for a dual elevator design
Platform: | Size: 6144 | Author: soumya | Hits:

[VHDL-FPGA-Verilog] call

Description: verilog实现电梯的召唤功能，在quantusII环境下运行，包含工程文件和其他子文件-verilog to achieve the elevator call functions in quantusII environment to run, including engineering documents, and other sub-documents
Platform: | Size: 176128 | Author: bailu | Hits:

[VHDL-FPGA-Verilog] elevator

Description: 三个八层电梯的控制器，verilog实现。内附有详细设计文档及源码。-The controller of three 8-level elevators, designed with Verilog. The design is detailedly represented in the DOC as well as the source code.
Platform: | Size: 272384 | Author: cc | Hits:

[VHDL-FPGA-Verilog] Verilog_zhinengdianti

Description: 很好的完善verilog代码，使用于智能电梯嵌入式开发和de2开发板爱好者-Very good perfect verilog code, used in intelligent elevator embedded development and de2 development board lovers
Platform: | Size: 208896 | Author: 阿桑德拉 | Hits:

[VHDL-FPGA-Verilog] elevator_v2

Description: 用verilog语言描述的模拟单电梯的运行过程。方向优先原则。(1)每层电梯入口处设有上下请求按钮（一楼只有上请求，6楼只有下请求），电梯内设有顾客到达层次的停站请求开关。 (2)电梯入口处设有电梯当前所处楼层指示装置及电梯运行模式(上升或下降)指示装置。 (3)电梯每2秒升(降)一层楼。 (4)电梯到达有停站请求的楼层，经过1秒电梯门打开，开门指示灯亮，开门3秒后，电梯进入关门中状态，提示乘客可以按下延迟关门按键，此时指示灯闪烁，2秒后电梯门关闭，电梯继续进行，直至执行完最后一个请求信号后停留在当前层。 (5)能记忆电梯内外所有请求，并按照电梯运行规则按顺序响应，每个请求信号保留至执行后消除。 (6)电梯运行规则（方向优先电梯调度算法）：当电梯处于上升模式时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到由下楼请求的最高层，然后进入下降模式。当电梯处于下降模式时则与上升模式相反。 (7)电梯初始状态为一楼等待状态。 -Simulation with verilog language to describe the operation of a single lift process. Direction priority principle. (A) each elevator entrance and down a request button (on the first floor only on request, 6th floor only under request), equipped with elevators to reach levels of customer request switch stops. (2) Lift the floor where the entrance to lift the current operating mode indicating device and lift (rising or falling) indicating devices. (3) Lift up every two seconds (lower) floor. (4) There are stops the elevator reaches the floor of the request, after one second the elevator doors opened, door lights, open the door three seconds later, the elevator into the closed state, suggesting that delayed passengers can press the button to close the door, then the indicator flashes, 2 seconds after the elevator doors closed, the elevator continues until the last request signal is executed after the stay in the current layer. (5) can memorize all requests outside the elevator
Platform: | Size: 3192832 | Author: 饶全成 | Hits:

[VHDL-FPGA-Verilog] Verilog_HDL_elevator

Description: Verilog实现的基于FPGA的五层楼电梯运行控制逻辑设计-FPGA-based five-story elevator control logic implemented in Verilog design
Platform: | Size: 18432 | Author: 柯家豪 | Hits:

[VHDL-FPGA-Verilog] 双电梯控制器

Description: 使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
Platform: | Size: 250880 | Author: gothic22 | Hits:

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