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Description: jpeg2000中的空间变换中的DWT，9/7有损小波正变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 wavelet is detrimental to transform, which is in the ADI blackfin535 DSP platform
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Size: 44032 |
Author: chenlei |
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Description: jpeg2000中的空间变换中的DWT，5/3无损小波逆变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 5/3 non-destructive inverse wavelet transform, which is in the ADI blackfin535 DSP platform
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Size: 41984 |
Author: chenlei |
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Description: jpeg2000中的空间变换中的DWT，9/7有损小波逆变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 inverse wavelet transform detrimental, which is in the ADI blackfin535 DSP platform
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Size: 43008 |
Author: chenlei |
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Description: 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸-This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission
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Size: 1467392 |
Author: chiahao |
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Description: 可用的基于小波的spiht算法，可以自己设定小波分解基数，做成人机交互界面，直观-Available to the SPIHT algorithm based on wavelet, wavelet decomposition can be set for the base, resulting in human-computer interaction interface, intuitive
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Size: 4057088 |
Author: 李雨 |
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Description: It s implementation on DWT. This was wrttend in verilog.
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Size: 3072 |
Author: vasantha Kumar |
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Description: deals with implementation of DWT
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Size: 612352 |
Author: ibbu |
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Description: 小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。-code of dwt
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Size: 413696 |
Author: 陈先生 |
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Description: VERILOG CODE FOR DWT IMAGE COMPRESSION
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Size: 16384 |
Author: vijayaragavan |
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Description: 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
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Size: 1473536 |
Author: asde198250 |
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