Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等
-including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc. Platform: |
Size: 616055 |
Author:ruan |
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Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation Platform: |
Size: 90116 |
Author:王雪松 |
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Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation Platform: |
Size: 90112 |
Author:王雪松 |
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Description: 一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using Platform: |
Size: 4096 |
Author:cloudy |
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Description:
Various memories for Xilinx and Altera FPGA devices. Single-port and
Dual-port versions with various numbers of read and write ports. Bundle
also includes read-first and write-first varieties with sync and async
clocks.
All memory components are generic, permitting the word width and number
of words to be specified easily.
Platform: |
Size: 14336 |
Author:Muhammed Hasan |
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Description: This manual describes the user interface respectively the dual-port memory for netX-based products
manufactured by Hilscher. Platform: |
Size: 814080 |
Author:kevin |
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Description: This manual describes the user interface respectively the dual-port memory for etX-based products manufactured by Hilscher.-This manual describes the user interface respectively the dual-port memory for etX-based products
manufactured by Hilscher. Platform: |
Size: 2468864 |
Author:kevin |
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Description: System Software DeviceNet
• loadable Firmware*
• System Configurator SyCon**
• OPC Server**
• CIF Device Driver
• Driver for SoftPLCs**
• GSD/EDS files
• Documentation
for all our Communication InterFaces CIF.
The Communication Interface handles the complete data exchange between the connected fieldbus stations and the PC. The data is available as process image in the dual-port memory of the CIF. The message oriented data exchange is handled via a mailbox in the dual-port memory.-System Software DeviceNet
• loadable Firmware*
• System Configurator SyCon**
• OPC Server**
• CIF Device Driver
• Driver for SoftPLCs**
• GSD/EDS files
• Documentation
for all our Communication InterFaces CIF.
The Communication Interface handles the complete data exchange between the connected fieldbus stations and the PC. The data is available as process image in the dual-port memory of the CIF. The message oriented data exchange is handled via a mailbox in the dual-port memory. Platform: |
Size: 162816 |
Author:Thomas. Eom |
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Description: 双口RAM 的乒乓存储结构（芯片型号CY7C09279）
应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging has verified] Platform: |
Size: 1024 |
Author:61408520 |
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Description: Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
-Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s. Platform: |
Size: 179200 |
Author:静水沉沙 |
Hits:
Description: 如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
-As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s. Platform: |
Size: 1024 |
Author:韩宇 |
Hits:
Search - dual port memory