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[Mathimatics-Numerical algorithms] metrix3

Description: 完成矩阵的输入、输出。具有相同行数和列数的矩阵间的加法、减法。符合矩阵乘法规则要求的矩阵间的乘法。方阵间的除法，方阵的求逆。矩阵的求转置矩阵等功能-Complete matrix of input and output. With the same number of rows and rows of the matrix between the adder, subtraction. In line with the requirements of the rules of matrix multiplication between matrix multiplication. Between square division, the inverse square. Matrix transpose matrix functions
Platform: | Size: 74752 | Author: | Hits:

[VHDL-FPGA-Verilog] fpdiv_vhdl

Description: 四位除法器的VHDL源程序-four division of VHDL source
Platform: | Size: 1024 | Author: 张庆辉 | Hits:

[AI-NN-PR] life_afly

Description: 本程序模拟细胞的自我繁殖，你会看到一个柔软的细胞诞生在电脑屏幕上，然后随着各个分子的撞击，细胞开始分裂，经过一段时间的演化，这个细胞会在溶液中把自己复制，然后这个过程会继续进行……。这种自我复制是在人工化学的基础上进行，比起原来的基于细胞自动机的自我复制更加形象逼真-the cell simulation of self-reproduction, you will see a soft cell birth on the computer screen, and then with all the percussive elements, cell division, after a period of evolution, the cells in the solution themselves copied, and then the process will continue ... . This self-reproduction of the artificial chemical basis, compared to the original cell-based automatic machine self-replication more vivid
Platform: | Size: 217088 | Author: 姚启迪 | Hits:

[VHDL-FPGA-Verilog] 除法器

Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50176 | Author: johnmad | Hits:

[ISAPI-IE] subr

Description: VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。 其实现方法是，将除法器分为两个状态：等待状态与运算状态。 开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Platform: | Size: 82944 | Author: aa | Hits:

[Other] 1.7运算器部件实验：除法器

Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
Platform: | Size: 151552 | Author: 李乐雅 | Hits:

[VHDL-FPGA-Verilog] 200632146671689

Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
Platform: | Size: 741376 | Author: lele | Hits:

[OpenGL program] openglxibaofenlie

Description: opengl的细胞分裂演示程序。可以当作教学使用。使用一定的生灭算法。-opengl demonstration of the cell division process. Can be used as teaching. The use of certain birth and death algorithm.
Platform: | Size: 1233920 | Author: 周东文 | Hits:

[Algorithm] vcmatrix

Description: 本源码包括矩阵运算的基本功能，包括矩阵加减、乘除、转置、求逆-the source of matrix of the basic functions, including matrix addition and subtraction, multiplication and division, to home, the inverse
Platform: | Size: 1024 | Author: | Hits:

[Books] networkengineerFLASH

Description: FLASH教学，包含内容：电路交换，分组交换，路由器工作原理，频分复用，时分复用，统计时分复用，虚拟局域网，中继器，网桥工作原理等。精彩形象，好东西不容错过，快来下载-FLASH teaching, including : circuit-switched, packet-switched, routers principle, frequency division multiplexing, TDM, TDM statistics, virtual LAN repeaters, bridges, and so on principle. Excellent image, good things not to be missed, Come Download
Platform: | Size: 525312 | Author: lixm | Hits:

[VHDL-FPGA-Verilog] verilog_Divide

Description: 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
Platform: | Size: 7168 | Author: | Hits:

[Algorithm] matrix_operation

Description: 本程序能完成矩阵的输入、输出。具有相同行数和列数的矩阵间的加法、减法。符合矩阵乘法规则要求的矩阵间的乘法。方阵间的除法，方阵的求逆。矩阵的求转置矩阵等功能。-this procedure can be completed matrix of input and output. Have the same number of rows and columns in the matrix between the additive and subtractive. Matrix multiplication with the requirements of the rules of the matrix multiplication. Lineup of the division, the inverse matrix. Matrix switch matrices for the function.
Platform: | Size: 74752 | Author: 李然 | Hits:

[VHDL-FPGA-Verilog] shift_div

Description: 基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
Platform: | Size: 1024 | Author: liqijun | Hits:

[Windows Develop] longnumber

Description: 长整数运算，实现长整数的加减乘除运算，高效、-Long integer calculations, the realization of a long integer addition and subtraction, multiplication and division operations, efficient and
Platform: | Size: 2048 | Author: | Hits:

[Algorithm] newton_raphson

Description: Summary: Newton-Raphson method for all real roots of the polynomial. MATLAB Release: R11 Description: This M-file calculates all the real roots of the given polynomial. It calls syn_division, a synthetic division function, and derivate, differentiation function. -Summary: Newton-Raphson method for all real roots of the polynomial. MATLAB Release: R11 Description: This M-file calculates all the real roots of the given polynomial. It calls syn_division, a synthetic division function, and derivate, differentiation function.
Platform: | Size: 2048 | Author: 风帆 | Hits:

[Embeded-SCM Develop] Qdiv

Description: 使用移位减法完成32位除法操作。适用于没有除法指令的嵌入式处理器。源码简单，适用-Use of translocation to complete 32-bit subtraction division operation. Does not apply to the embedded processor division instruction. Source is simple, the application of
Platform: | Size: 1024 | Author: 10664417 | Hits:

[MPI] 18-1

Description: 矩阵转置并行计算，需要至少4个处理器，采用块棋盘划分方法-Matrix transpose parallel computing, require at least four processors, the use of block division method chessboard
Platform: | Size: 2048 | Author: 我依然在 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] division

Description: 很实用的一个分频带码，包括奇分频，偶分频，占空比为50％的奇分频,实际工程中很实用-Very useful to a sub-band code, including the odd sub-frequency, dual frequency, duty cycle 50 of the odd sub-frequency, the actual works in very practical
Platform: | Size: 290816 | Author: ecomputer | Hits:

[Other] springer_-_orthogonal.frequency.division.multiplex

Description: ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING FOR WIRELESS COMMUNICATIONS
Platform: | Size: 11986944 | Author: 施云涛 | Hits:
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