Search - divider verilog fractional

[VHDL-FPGA-Verilog] divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: | Size: 3072 | Author: 刘蒲霞 | Hits:

[ARM-PowerPC-ColdFire-MIPS] 5956447divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
Platform: | Size: 3072 | Author: wfwef | Hits:

[VHDL-FPGA-Verilog] divider16

Description: 16位小数除法器verilog源码，可综合的，已经仿真过。-16bit fractional numeral divider verilog source
Platform: | Size: 1024 | Author: maxwellqq | Hits:

[VHDL-FPGA-Verilog] decimal_divison

Description: 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
Platform: | Size: 558080 | Author: 冯正 | Hits:

[Other] Div

Description: 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
Platform: | Size: 813056 | Author: 洪依 | Hits:

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[VHDL-FPGA-Verilog] divider

[ARM-PowerPC-ColdFire-MIPS] 5956447divider

[VHDL-FPGA-Verilog] divider16

[VHDL-FPGA-Verilog] decimal_divison

[Other] Div

[VHDL-FPGA-Verilog] xiaoshu

[Other Embeded program] fen-pin-Verilog(2013-06-25-09.54.41)

[VHDL-FPGA-Verilog] clk_generator

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