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Description: 基于AT89C51的MP3播放器源码和电路图-AT89C51 based MP3 player and source circuit
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Size: 894976 |
Author: 钱海良 |
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Description: 基于at89s51单片机的数字钟程序
有闹钟秒表等功能-AT89S51 MCU-based digital clock program has features such as alarm clock stopwatch
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Size: 5120 |
Author: licheng |
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Description: 一个简单的数字时钟程序，其中的date类派生于MFC CStatic 基类-A simple digital clock procedures, in which category the date derived from MFC CStatic base class
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Size: 122880 |
Author: litingjiu |
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Description: 5800C Fm芯片资料和驱动代码
技术特点：
*国内首颗采用CMOS工艺的调频收音机芯片；
*驱动能力强，可直接驱动耳机及放大器；
*功耗低，比国外先进方案还低1mA；
*频率覆盖从76M-108M的各国调频波段；
*高度集成度，所需外围器件数为零；
*强大的LOW-IF数字音频结构；
*强大的数字信号处理技术（DSP）,实现自动频率控制和自动增益控制；
*数字自适应噪声抑制
接受灵敏度高、音质出色、立体声效果优异；
*支持重低音，可调式电台搜寻、柔软静音和混音等功能；
*只需一个32.768K晶振作为参考时钟；
*支持I2C和SPI数字接口，支持I2S音频接口，可以配合所有多媒体处理芯片；
*可调去加重（50／75 us) ；
*模拟和数字音量控制；
*线性模拟输出电压；
*两线和三线控制接口模式；
*封装面积： 4×4mm，24-pin QFN-5800C Fm chip code data and drive
Technical characteristics:
* Domestic first CMOS process using the FM radio chip
* Drive ability, and can directly drive headphones and amplifier
* Low power consumption, advanced program than lower 1mA
* Frequency coverage from 76M-108M FM band of countries
* A high degree of integration, necessary to zero the number of peripheral devices
* LOW-IF powerful digital audio structure
* A powerful digital signal processing technology (DSP), automatic frequency control and AGC
* Digital Adaptive Noise Reduction
Acceptance of high sensitivity, excellent sound quality, excellent stereo sound effects
* To support the heavy bass, adjustable radio search, soft mute and blend functions
* Only one 32.768K crystal as a reference clock
* Support for I2C and SPI digital interface to support I2S audio interface will be in line with all the multimedia processing chip
* Adjustable de-emphasis (50/75 us)
* Analog and digital volu
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Size: 1367040 |
Author: 文社 |
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Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。
CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions.
CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
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Size: 129024 |
Author: 623902748 |
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Description: 单片机的数字钟设计,毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-Microcontroller digital clock design, graduate design with Protel map, the source code through the use proteus software simulation, with a Bi-based papers
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Size: 585728 |
Author: fengxinlong |
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Description: m sure you ve seen analog clocks, digital clocks and maybe even binary clocks! Traditionally, analog clocks (or watches) display time by a continuous motion of two (hour, minute) or three (second) rotating pointers pointing to numbers arrayed on a circular dial. - m sure you ve seen analog clocks, digital clocks and maybe even binary clocks! Traditionally, analog clocks (or watches) display time by a continuous motion of two (hour, minute) or three (second) rotating pointers pointing to numbers arrayed on a circular dial.
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Size: 7168 |
Author: ishan |
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Description: A timing error detector for Communication systems with simulink.
# Required versions Matlab 5.2.1, Simulink 2.2.1
# File description
1. ti_det1.m (simulink version 5.2.1)
An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller,
Timing recovery in digital synchronous data receivers,
IEEE Trans. Comun., vol COM-24, no. 5, May 1976.
2. m_delay3.m (related m-file)
An s-function operating as sample and hold with clock port.
3. test1.mdl
A timing recovery system to test the timing detector.
-A timing error detector for Communication systems with simulink.
# Required versions Matlab 5.2.1, Simulink 2.2.1
# File description
1. ti_det1.m (simulink version 5.2.1)
An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller,
Timing recovery in digital synchronous data receivers,
IEEE Trans. Comun., vol COM-24, no. 5, May 1976.
2. m_delay3.m (related m-file)
An s-function operating as sample and hold with clock port.
3. test1.mdl
A timing recovery system to test the timing detector.
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Size: 156672 |
Author: juyayayo |
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Description: its a M file. Digital clock
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Size: 1024 |
Author: bala |
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Description: 基于51单片机数码管的电子时钟，时间精确-Based on 51 single chip microcomputer digital tube digital clock, time accurately
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Size: 1024 |
Author: 刘艺成 |
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Description: 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.
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Size: 119808 |
Author: ai |
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Description: 给定当前的时间，请用英文的读法将它读出来。
时间用时h和分m表示，在英文的读法中，读一个时间的方法是：
如果m为0，则将时读出来，然后加上“o clock”，如3:00读作“three o clock”。
如果m不为0，则将时读出来，然后将分读出来，如5:30读作“five thirty”。
时和分的读法使用的是英文数字的读法，其中0~20读作：
0:zero, 1: one, 2:two, 3:three, 4:four, 5:five, 6:six, 7:seven, 8:eight, 9:nine, 10:ten, 11:eleven, 12:twelve, 13:thirteen,
14:fourteen, 15:fifteen, 16:sixteen, 17:seventeen, 18:eighteen, 19:nineteen, 20:twenty。
30读作thirty，40读作forty，50读作fifty。
对于大于20小于60的数字，首先读整十的数，然后再加上个位数。如31首先读30再加1的读法，读作“thirty one”。
按上面的规则21:54读作“twenty one fifty four”，9:07读作“nine seven”，0:15读作“zero fifteen”。-Given the current time, please use English law will read it out.
H and minutes time m said, in English law, read a time method is:
If m is 0, will read it out, and then add o clock, if 3:00 read three o clock.
If m is not 0, will read it out, and then read it out, such as 5:30 read five thirty .
And points of law is used when the English pronunciation of the new digital, including 0 ~ 20 read:
Zero, zero, 1: one, two, two, three, three, four, four, five, five, six, six, seven, seven, eight, eight, nine, nine, ten, ten, eleven, eleven, twelve, twelve, thirteen, thirteen.
15:14: fourteen, fifteen, sixteen, sixteen, 17: seventeen, eighteen: eighteen, 19: nineteen, 20: twenty.
Read for thirty 30, 40 read forty, fifty read looking.
For more than 20 less than the number of 60, first read the whole ten number, and then combined with single digits.Such as 31 first read 30 plus 1 law, pronounced thirty one .
According to the rules above 21:54 read twenty one looking four , 9:07
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Size: 1024 |
Author: fairy |
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Description: 南工程数电课程设计多功能数字钟优秀设计 所有原理图 电路图 实际接线图都在哦-Southern electrical engineering curriculum design number of outstanding design multifunction digital clock schematic circuit diagram of all the actual wiring diagram are oh
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Size: 447488 |
Author: 周烨桐 |
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Description: 用stc12c2052ad为单片机内核，内附图片，四位数码管显示，12m晶振，完美时钟，让我们“hi”起来！-For single chip microcomputer with stc12c2052ad kernel, enclose pictures, the four digital tube display, 12 m crystals, perfect clock, let us hi !
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Size: 3072 |
Author: 王昱顺 |
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Description: e Handbook Entry
Communication concepts: Fourier transforms, random signals, Transmitter
and receiver filters, matched filter, Nyquist criterion. Digital Modulation schemes:
M-ary ASK, QPSK, FSK, CPM, spectral analysis of modulated signals, ML and
MAP detectors, signal space methods, bit error rate analysis. Digital Receivers:
carrier and clock synchronisation. Information theory: entropy, channel capacity,
source coding. Channel Coding: block codes, convolutional codes.
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Size: 17408 |
Author: Khan17
|
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Description: 设计一个简易数字信号ASK调制系统。系统数字基带信号V1为m序列伪随机信号，载波信号V2为正弦波周期信号，V3为V1经二进制幅移键控调制后的输出。系统输入为CLOCK和RESET信号，CLOCK是系统时钟信号，上升沿触发。RESET为系统异步复位信号，高有效。(A simple digital signal ASK modulation system is designed. The system digital baseband signal V1 is m sequence pseudo random signal, carrier signal V2 is sine wave periodic signal, V3 is V1 after binary amplitude shift keying modulation output. The system inputs are CLOCK and RESET signals, CLOCK is the system clock signal and the rising edge triggers. RESET is a system asynchronous reset signal, which is highly effective.)
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Size: 163840 |
Author: mms‘’ |
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Description: 一个16QAM数字调制电路，包括时钟生成电路，m伪随机序列生成电路，串并转换电路，电平映射电路、载波信号发生电路、ASK幅度调制电路及加法器(A 16QAM digital modulation circuit, including clock generation circuit, m pseudo-random sequence generation circuit, serial parallel conversion circuit, level mapping circuit, carrier signal generation circuit, ask amplitude modulation circuit and adder.)
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Size: 2685952 |
Author: 独行的云 |
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