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[VHDL-FPGA-Verilog] vhdl-devider

Description: 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
Platform: | Size: 1024 | Author: tony | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Clock devider in VHDL code
Platform: | Size: 2048 | Author: Haitham | Hits:

[Software Engineering] VHDLsourcecode

Description: source code for counter, freq devider, traffic light, stepper motor, flipflop
Platform: | Size: 2048 | Author: ibnudahlan | Hits:

[VHDL-FPGA-Verilog] debouncer_vhdl

Description: debouncer in vhdl with clock devider parameter and number of inputs
Platform: | Size: 69632 | Author: Andrey | Hits:

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